DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of U.S. Patent No. 12,355,440.
Although the claims at issue are not identical, they are not patentably distinct from each other because the US Patent claims a semiconductor device in which a controller generate a trimming code. The instant application claims recite substantially the same subject matter, differing only in that a controller generate a first trimming code and a second trimming code. The additional limitation requiring the controller to generate a first trimming code and a second trimming code does not render the claimed invention patentably distinct over the US Patent claims. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of US Patent application to generate more than one signal from the same controller is predictable and routine modification. In the absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Accordingly, the claims of the instant application are not patentably distinct from the claims of the Patent application.
Regarding claims 1 and 8, see table below.
Instant application 19/227501
US Patent No. 12,355,440
1. A semiconductor device, comprising: a process monitor circuit, configured to measure process information of the semiconductor device; a controller, electrically connected to the process monitor circuit, and configured to generate a first trimming code and a second trimming code based on the measured process information; and an output buffer, electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the first trimming code and the second trimming code, respectively, wherein the output buffer comprises: a first output driver transistor, a second output driver transistor, a first feedback capacitance, and a second feedback capacitance, wherein the first feedback capacitance is coupled between a gate and a first terminal of the first output driver transistor, and the second feedback capacitance is coupled between a gate and a first terminal of the second output driver transistor.
1. A semiconductor device, comprising: a process monitor circuit, configured to measure process information of the semiconductor device; a controller, electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information; and an output buffer, electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code, wherein the output buffer comprises: a first output driver transistor, a second output driver transistor, a first feedback capacitance, and a second feedback capacitance, wherein the first feedback capacitance is coupled between a gate and a first terminal of the first output driver transistor, and the second feedback capacitance is coupled between a gate and a first terminal of the second output driver transistor.
8. An output buffer circuit, comprising: an oscillation circuit, configured to generate an oscillation frequency; a controller, electrically connected to the oscillation circuit, and configured to generate a first trimming code and a second trimming code based on the oscillation frequency generated by the oscillation circuit; and an output buffer, electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the first trimming code and the second trimming code, respectively, wherein the output buffer comprises: a first output driver transistor, a second output driver transistor, a first feedback capacitance, and a second feedback capacitance, wherein the first feedback capacitance is coupled between a gate and a first terminal of the first output driver transistor, and the second feedback capacitance is coupled between a gate and a first terminal of the second output driver transistor.
7. An output buffer circuit, comprising: an oscillation circuit, configured to generate an oscillation frequency; a controller, electrically connected to the oscillation circuit, and configured to generate a trimming code based on the oscillation frequency generated by the oscillation circuit; and an output buffer, electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code, wherein the output buffer comprises: a first output driver transistor, a second output driver transistor, a first feedback capacitance, and a second feedback capacitance, wherein the first feedback capacitance is coupled between a gate and a first terminal of the first output driver transistor, and the second feedback capacitance is coupled between a gate and a first terminal of the second output driver transistor.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,355,440, and in view of Sasaki (US 2024/0195358).
Regarding claim 17, see table below.
Claim 17 of application 19/227,501
(APP’ 501)
Claim 15 of US 12,355,440
(PAT’ 440)
17. An output buffer circuit, comprising: an oscillation circuit, configured to generate an oscillation frequency;
a controller, electrically connected to the oscillation circuit, and configured to generate a trimming code based on the oscillation frequency generated by the oscillation circuit; and
an output buffer, electrically connected to the controller, and configured to calibrate a first bias current and a second bias current by adjusting a first bias resistance and a second bias resistance based on the trimming code, respectively, wherein the output buffer comprises a first adjustable resistor circuit configured to output the first bias resistance, and a second adjustable resistor circuit configured to output the second bias resistance.
15. An output buffer circuit, comprising: an oscillation circuit, configured to generate an oscillation frequency;
a controller, electrically connected to the oscillation circuit, and configured to generate a trimming code based on the oscillation frequency generated by the oscillation circuit; and
an output buffer, electrically connected to the controller, and configured to adjust a first bias resistance and a second bias resistance based on the trimming code, wherein the output buffer comprises a first adjustable resistor circuit configured to output the first bias resistance, and a second adjustable resistor circuit configured to output the second bias resistance.
Regarding claim 17, PAT’ 440 fails to disclose wherein output buffer configured to calibrate a first bias current and a second bias current.
However, Sasaki in the same field of endeavor discloses [see figs. 1 and 9H] wherein to adjust a first bias current [40, fig. 9H] and a second bias current [40, fig. ] based on a trimming code [tc_trim/f_trim, fig. 1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate the incorporating a first bias current and a second bias current as taught in Sasaki in order to utilize known adjustable bias current.
Claims 2-5, 9 -16 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-4, 6, 8-14 and 16-17 and 19-20 of U.S. 12,355,440.
Allowable Subject Matter
Claims 6-7 would be allowable upon timely filing of a terminal disclaimer.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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