DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 7 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8 and 10 of U.S. Patent No. 12,354,633. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar claim language.
The claims are compared below:
Present claim 1
Claim 8 of patent 12,354,633
An integrated chip, comprising:
a lower electrode;
a high-k dielectric material disposed over the lower electrode;
an upper electrode disposed over a central region of the high-k dielectric material;
and a dielectric spacer arranged on a peripheral region of the high-k dielectric material, wherein the high-k dielectric material comprises non-zero concentrations of a tetragonal phase and a monoclinic phase, t
he non-zero concentrations of the tetragonal phase and the monoclinic phase being lower than a concentration of orthorhombic phase within the high-k dielectric material.
An integrated chip, comprising:
a lower electrode;
a high-k material structure disposed over the lower electrode;
an upper electrode disposed over a central region of the high-k material structure;
and a stressed dielectric spacer arranged on a peripheral region of the high-k material structure, wherein the high-k material structure has an orthorhombic phase concentration that varies between the central region and the peripheral region
wherein the ferroelectric layer further comprises non-zero concentrations of a tetragonal phase and a monoclinic phase, the non-zero concentrations of the tetragonal phase and the monoclinic phase being lower than a concentration of the orthorhombic phase within the ferroelectric layer.
Present claim 7
Claim 10 of 12,354,633
An integrated chip, comprising: a lower electrode
a dielectric data storage structure disposed over the lower electrode; an upper electrode disposed over a central region of the dielectric data storage structure;
and a dielectric spacer arranged over a peripheral region of dielectric data storage structure,
wherein the dielectric data storage structure has a minimum orthorhombic phase concentration that is greater than approximately 40%.
A device, comprising: a bottom electrode;
a ferroelectric layer disposed on the bottom electrode; a top electrode disposed on the ferroelectric layer;
and a spacer layer disposed on the ferroelectric layer and adjacent to the top electrode, wherein the ferroelectric layer has a higher concentration of orthorhombic phase within an edge region than within a central region.
wherein a concentration of the orthorhombic phase within the central region is greater than approximately 40%
Allowable Subject Matter
Claims 14-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 14-20, the prior art does not teach “…forming a lower electrode layer over a substrate; forming a high-k data storage layer over the lower electrode layer; forming an upper electrode over the high-k data storage layer; forming one or more stressed sidewall spacers laterally surrounding the upper electrode; increasing an orthorhombic phase concentration within parts of the high-k data storage layer after forming the one or more stressed sidewall spacers; and patterning the high-k data storage layer and the lower electrode layer outside of the upper electrode and the stressed sidewall spacer to form a high-k data storage structure and a lower electrode.”
Claims 2-6 and 8-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Song (2024/0130136], Huang (2022/0285519), Zhu (2009/0108378) and Arghavani (2008/0061285).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW SASINOWSKI whose telephone number is (571)270-5883. The examiner can normally be reached 7am - 4pm, Mon.-Fri. EST.
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/ANDREW SASINOWSKI/Primary Examiner, Art Unit 2625