Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7, 9, 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al. US 2024/0324283.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Kang et al., fig. 8, discloses a display device (FIGS. 1 to 4, a display device 100 may include a display panel 110) comprising: a display panel including a pixel (The display panel 110 may include a plurality of pixel circuits 111), wherein the pixel includes: a light emitting element (OLED); a first transistor (T1) connected between the light emitting element (OLED) and a first driving voltage line (ELVDD), the first transistor that operates based on a potential at a first node (N2); a second transistor (T2) connected between a data line (DL) and a first electrode of the first transistor (T1, T2), and the second transistor that receives a first scan signal through a first scan line (SL1); a third transistor (T3) connected between the first node (N2) and a second electrode of the first transistor (T1), and the third transistor (T3) that receives a second scan signal through a second scan line (SL4); a fourth transistor (T4) connected between the first node (N2) and a first initializing voltage line (Vint1), and the fourth transistor (T4) that receives a third scan signal through a third scan line (SL3); a storage capacitor (Cst) connected between the first node (N2) and the first driving voltage line (ELVDD); a first boost capacitor (Cbt) connected between the first node (N2) and the first scan line (SL1); and a second boost capacitor (Nbt1) connected between the first node (N2) and the second scan line (Nbt).
Regarding claim 2, Kang et al., fig. 8, discloses the display device of claim 1, wherein the second boost capacitor includes: a first sub-boost capacitor and a second sub-boost capacitor connected in series between the first node and the second scan line (see Cbt and Nbt, N2 and SL4).
Regarding claim 7, Kang et al., fig. 8, discloses the display device of claim 1, wherein the first scan signal is activated during a data write period, the second scan signal is activated during a compensating period, the data write period and the compensating period overlap each other, each of the data write period and the compensating period is a low level period, and a terminating time point of the compensating period is the same as or follows a terminating time point of the data write period (see pars. 46-48, 62, 70).
Regarding claims 9, 20, Kang et al., fig. 8, discloses a display device comprising: an element layer including a light emitting element (OLED); and a circuit layer including a pixel circuit unit (pixel circuits 111) connected to the light emitting element (OLED), wherein the circuit layer includes: a first transistor (T1) including a gate electrode connected to a first node (N2), a first electrode connected to a second node (N1), and a second electrode (T2) connected to a third node (N3); a second transistor (T2) including a gate electrode connected to a first scan line (SL1), a first electrode (T1) connected to a data line (DL), and a second electrode (T2) connected to the second node (T2); a third transistor (T3) including a gate electrode connected to a second scan line (SL4), a first electrode connected to the third node (N3), and a second electrode connected to the first node (N2); a fourth transistor (T4) including a gate electrode connected to a third scan line (SL3), a first electrode connected to a first initializing voltage line (Vint1), and a second electrode connected to the first node (N2); a first capacitor electrode extending from the gate electrode of the first transistor (Cbt); a second capacitor electrode which faces the first capacitor electrode to form a storage capacitor (Cst), and connected to a first driving voltage line (ELVDD); and an additional gate electrode connected to the gate electrode of the first transistor, and overlapping the first scan line to form a first boost capacitor (Nbt), and the additional gate electrode is disposed on a layer different from a layer for the gate electrode of the first transistor, the second capacitor electrode, and the first scan line (see fig. 8, pars. 62, 70).
Allowable Subject Matter
Claims 3-6, 8, 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest that the display device of claim 1, wherein the pixel further includes: a fifth transistor connected between the first electrode (T5) of the first transistor and the first driving voltage line (ELVDD), and the first transistor (T1) that receives a light emitting control signal through a light emitting control line (OLED); a sixth transistor (T6) connected between the second electrode of the first transistor (T1) and the light emitting element (OLED), and the second transistor (T2) that receives the light emitting control signal through the light emitting control line (OLED); a seventh transistor (T7) connected between the light emitting element (OLED) and a second initializing voltage line (Vint2), and the third transistor (T3) that receives a fourth scan signal (SL2) through a fourth scan line; and an eighth transistor Regarding claim 2, Kang et al., fig. 8, discloses the (T8) connected between the first electrode of the first transistor and a bias voltage line, and the fourth transistor that receives the fourth scan signal through the fourth scan line, and each of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors is a low-temperature polycrystalline silicon (LTPS) transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VAN N CHOW/Primary Examiner, Art Unit 2627
Prosecution Insights