DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on May 22th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election with traverse of Invention I (claims 2-10) in the reply filed on May 22th, 2026 is acknowledged. The traversal is on the ground(s) that the office fail to show serious search and/or examination burden on groups I and II and there is no serious burden for search/examination of groups I and II. This is not found persuasive because claim 22 recites specific methods of forming insulating material, thinning, removing carrier and simulating which is not reciting in claim 1 and these limitations requires different field of search, different interpretation and different art rejections.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 5-9, 13-14 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng et al. (Pub. No.: US 2018/0261666 A1), hereinafter as Zeng.
Regarding claim 17, Zeng discloses a power semiconductor device in Figs. 4 and 2 with a first surface (top surface of layer 74) and a second surface (bottom surface of N-- layer) opposite to each other in a first dimension of three orthogonal dimensions (Y-direction) (see Figs. 2 and 4 and [0037], [0045]), wherein an emitter electrode (emitter 18) is operatively connected to the first surface and a collector electrode
(Collector) is operatively connected to the second surface, comprising: a drift layer of a first conductivity type (combination of layer 70) located between the first surface and the second surface, and having a first doping concentration (having concentration of N+ and N-) (see Fig. 4 and [0035], [0045]); a source region of the first conductivity type (layer
74) operatively connected to the emitter electrode, with a second doping concentration
greater than the first doping concentration (layer 74 having concentration of N++ is greater than a concentration of N- of layers 22), and having a first edge (right edge of
layer 74 adjacent to trench 66) in a second dimension of the three orthogonal
dimensions (in Z-direction) (see Fig. 4 above and [0045]); a first base layer of a second conductivity type (layer 72) enclosing the source region, and having a third doping concentration (concentration of P type) (see [0045]); a second base layer of the second conductivity type (layer 75) located within the first base layer and extending towards the second surface below the source region, having a fourth doping concentration greater than the third doping concentration (concentration of P+ layer is greater than concentration P-well), and having at least a region/point operatively connected to the emitter electrode via a contact opening (opening within dielectric layer) (see Fig. 4 and [0045]); a first gate electrode of a heavily doped polycrystalline layer or a metal-containing layer (lateral portion of gate 60 as shown in annotated Fig. 4 above), arranged on top of the first surface, electrically insulated from the first base layer, the source region and the drift layer by a first insulating layer (horizontal portion of thin Gate Oxide 62) (see Fig. 4 and [0035], [0045]), a horizontal channel is formable (horizontal channel formed during operation between emitter 18, layer 74, layer 72 and layers 70/22) between the emitter electrode, the first source region, the first base layer and the drift layer; a plurality of trench regions (plurality of trenches 66), each comprising a second gate electrode (vertical extension of gate 60) and a second insulating layer (horizontal portion of thin Gate Oxide thin gate oxide 62), the second insulating layer electrically insulating the second gate electrodes from the first base layer, the second base layer, the source region and the drift layer, wherein at least one of the trench regions abut the source region (see Fig. 4), and wherein the plurality of trench regions do not overlap the contact opening in their longitudinal extension direction (see Fig. 4 and [0045]); a third insulating layer (thick dielectric layer) electrically insulating the emitter electrode from the first gate electrodes (see Fig. 4); and a floating layer of the second conductivity type (layer 40) surrounding the bottom regions of one or more of the trench regions (see Fig. 4 and [0038]); wherein the source region, the first base layer, the second base layer, and the first gate electrode extend longitudinally in a top plane view in a third dimension of the three orthogonal dimensions (X-direction) (layers 74, 75, 72 and vertical portion of gate 60 having a length extending in the X-direction) (see Fig. 4 above); wherein the plurality of trench regions extends in a top plane view at an angle greater than 0 degrees with respect to the third dimension (trenches 66 having length extending at least in Z-direction making 45 degree angle with X-direction) (see Fig. 4).
Regarding claim 5, Zeng discloses a power semiconductor according to claim 17, wherein the first and the plurality of second gate electrodes are electrically connected (all gates 60 are electrically connected during operation within a closed circuit).
Regarding claim 6, Zeng discloses a power semiconductor according to claim 17, wherein at least a portion of the plurality of second gate electrodes are electrically connected to the emitter electrode (all gates 60 electrically connected to emitter 18 during operation within a closed circuit).
Regarding claim 7, Zeng discloses a power semiconductor according to claim 17, wherein at least a portion of the plurality of second gate electrodes are electrically floating (portions of all gate 60 are electrically floating if the gate 60 is not electrically connecting to power source).
Regarding claim 8, Zeng discloses a power semiconductor according to claim 17, wherein: the first gate electrode is formed out of a plurality of electrodes embedded in a plurality of trench regions (plurality of vertical portions of gates 60), arranged on the first surface and extending in the third dimension in a top plane view (extending in X-direction) (see Fig. 4 above); characterized in that, a vertical MOS channel is formable by the first gate electrode between the emitter electrode, the source region, the first base layer, and the drift layer (channel formed when IGBT turns on); and, a plurality of second gate electrodes being different than the plurality of the first gate electrode trench regions (plurality of horizontal portions of gates 60 different from vertical portions), and extending in a dimension oriented at an angle greater than 0 with respect to the third dimension (extending in the Z-direction at 90 degree angle with the X-direction) (see Fig. 4 above).
Regarding claim 9, Zeng discloses a power semiconductor according to claim 17, wherein an enhancement layer of the first conductivity type (layer 70) is arranged between the drift layer and the first base layer, thereby separating the drift layer and the first base layer (see Fig. 4 and [0046]).
Regarding claim 13, Zeng discloses a power semiconductor according to claim 17, comprising: a buffer layer of the first conductivity type (N-buffer layer) with a higher doping concentration than the drift layer, arranged between the drift layer and the collector electrode (N-buffer layer has concentration of N-type and higher than the concentration of N-/N—layer 22).
Regarding claim 14, Zeng discloses a power semiconductor according to claim 17, comprising: a collector layer of the second conductivity type (P+ layer/P+ substrate) arranged on the second surface between the drift layer and the collector electrode (between N-/N--layer 22 and Collector) (see Fig. 4 and [0016]); characterized in that the collector layer is formed before, during, or after a MOS cell process (one of scenario would happen); or comprising: a buffer layer of the first conductivity type with a higher doping concentration than the drift layer (N-buffer layer has concentration of N-type and higher than the concentration of N-/N—layer 22), which buffer layer is arranged on the second surface between the drift layer and the collector electrode; and a collector layer of the second conductivity type (P+ layer/P+ substrate), which is arranged on the second surface between the buffer layer and the collector electrode; characterized in that the buffer and collector layers are formed before, during, or after the MOS cell process (see Fig. 4).
Furthermore, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 14 is directed to a device, the method of forming the collector layer is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…is formed before, during, or after a MOS cell process” stated in claim 14 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 16, Zeng discloses a power semiconductor according to claim 17, wherein the power semiconductor device has a stripe layout design or a cellular layout design (cell layout) (see Fig. 4 and [0045]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-5 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. (Pub. No.: US 2018/0040658 A1), hereinafter as KANG, and further in view of CHEN et al. (Pub. No.: US 2019/0067244 A1), hereinafter as CHEN.
Regarding claim 2, KANG discloses a bonded structure in upside-down view of Fig. 1B, comprising: a first die (image sensor chip 500 and re-distribution layer 400) comprising an optical device (image sensor chip 500), wherein the first die comprises a first surface (exposed surface of re-distribution layer 400) that comprises a first region (middle region of the exposed surface including first pads 451) and a second region (outer region of the exposed surface) that is laterally adjacent to the first region, wherein the first region comprises a first nonconductive field region (regions between first pads 451) and a plurality of first conductive interconnections (plurality of first pads 451) (see [0036], [0042-0043]); an electronic integrated circuit die (chip 200) having a second surface (exposed surface of layer 210) that comprises a second nonconductive field region (region between chip pads 201) and a plurality of second conductive interconnections (plurality of chip pad 201), wherein the first die and the electronic integrated circuit die are bonded together (bonded by connection terminal CT) such that the plurality of first conductive interconnections are bonded to the plurality of second interconnections and the first nonconductive field region is bonded (bonded by mold layer 300) to the second nonconductive field region and wherein the electronic integrated circuit die does not cover the second region (see [0036] and [0042]); and an insulating material (molding layer 300) over the second region (see [0038]).
KANG fails to disclose the first die and the electronic integrated circuit die are hybrid bonded together such that the plurality of first conductive interconnections are directly bonded to the plurality of second interconnections and the first nonconductive field region is directly bonded to the second nonconductive field region.
CHEN discloses a bonded structure in Fig. 1 comprising a first die (substrate 101, layer 101b and conductive member 101c) and an electronic integrated circuit die (die 102a, layer 102b and conductive member 102c) are hybrid bonded together such that a plurality of first conductive interconnections (plurality of conductive members 101c) are directly bonded to a plurality of second interconnections (plurality of conductive members 102c) and a first nonconductive field region (surface of layer 101b at interface 102d) is directly bonded to a second nonconductive field region (surface of layer 102b at interface 102d) (see [0015], [0019-0020], [0025] and [0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the bonding between the first die and the electronic integrated circuit die of KANG to be hybrid bonding as same as the bonded structure of CHEN because the teaching of CHEN discloses the bonding between two electronic circuit die can be hybrid for directly bonding or indirectly bonding method using solder ball and molding layer and hybrid bonding would lower power consumption, improved signal integrity and enhancing thermal performance.
Regarding claim 3, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 2, wherein the electronic integrated circuit die (chip 200) comprises a side surface (a side surface of chip 200) and wherein the insulating material directly contacts the side surface (mold layer 300) (see Fig. 1B).
Regarding claim 4, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 2, KANG fails to disclose the insulating material comprising silicon oxide. However, CHEN discloses the bonded structure comprising an insulating material (molding 104) comprises silicon oxide (see Fig. 1 and [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the insulating material of KANG to have silicon oxide as same as the insulating material of CHEN because the modified structure would provide high thermal stability and promote excellent adhesion.
Regarding claim 5, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 2, wherein the electronic integrated circuit die comprises a back surface (the surface of chip 200 facing substrate 100), wherein the insulating material comprises an upper surface, and wherein the upper surface and the back surface are substantially co-planar (see upside-down view of Fig. 1B).
Regarding claim 6, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 2, wherein the electronic integrated circuit die comprises a back surface and wherein the insulating material at least partially covers the back surface (during intermediate process when forming mold layer 300, the mold layer 300 will cover at least partially the back surface of chip 200) (see Fig. 6D, KANG and [0076]).
Regarding claim 7, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 2, wherein the first die comprises a first side surface (sidewall of chip 500 and layer 400), the insulating material comprises a second side surface (sidewall of molding layer 300), and wherein the first and second side surfaces are coplanar with each other (see Fig. 1B).
Regarding claim 8, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 7, wherein the electronic integrated circuit die comprises a third side surface (sidewall of chip 200) and wherein the insulating material extends between the third side surface and the second side surface (see Fig. 1B).
Regarding claim 9, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 7, wherein the first and second side surfaces at least partially define an outer surface of the bonded structure (see Fig. 1B).
Regarding claim 10, the combination of KANG and CHEN Zeng discloses the bonded structure of claim 7, wherein the first die comprises first active circuitry (circuit layer 503) electrically coupled to the plurality of first conductive interconnections (pad 452) (see KANG, Fig. 1B and [0041]), wherein the electronic integrated circuit die comprises second active circuitry (integrated devices not shown in circuit pattern 210) electrically coupled to the plurality of second conductive interconnections (pad 201) (see KANG, Fig. 1B and [0037]), and wherein the first active circuitry and the second active circuitry are electrically coupled together with the pluralities of first and second conductive interconnections (see Fig. 1B of KANG).
Regarding claim 11, KANG discloses a method of forming a bonded structure in upside-down view of Fig. 6A-6D, comprising: providing a substrate (image sensor chip 500 and re-distribution layer 400) that comprises an optical device (image sensor chip 500), where the substrate comprises a first surface (exposed surface of re-distribution layer 400) that comprises a first region (middle region of the exposed surface including first pads 451) and a second region (outer region of the exposed surface) that is laterally adjacent to the first region, wherein the first region comprises a first nonconductive field region (regions between first pads 451) and a plurality of first conductive interconnections (plurality of first pads 451) (see Figs. 6A-6B [0036], [0042-0043], [0069-0073]); providing an electronic integrated circuit die (chip 200) having a second surface (exposed surface of layer 210) that comprises a second nonconductive field region (region between chip pads 201) and a plurality of second conductive interconnections (plurality of chip pad 201); bonding the second surface to the first surface such that the plurality of first conductive interconnections are indirectly bonded to the plurality of second conductive interconnections (bonded by connection terminal CT) and the first nonconductive field region is indirectly bonded to the second nonconductive field region(bonded by mold layer 300) (see Fig. 6C, [0036], [0042] and [0074]); and forming an insulating material (molding layer 300) over the second region (see Fig. 6D and [0076]).
KANG fails to disclose the bonding is hybrid bonding to make the second surface to the first surface such that the plurality of first conductive interconnections are directly bonded to the plurality of second conductive interconnections and the first nonconductive field region is directly bonded to the second nonconductive field region
CHEN discloses a method of forming a bonded structure in Fig. 1 comprising providing a substrate (substrate 101, layer 101b and conductive member 101c) and an electronic integrated circuit die (die 102a, layer 102b and conductive member 102c); hybrid bonding a second surface (surface of layer 102b) to a first surface (surface of layer 101b) such that such that a plurality of first conductive interconnections (plurality of conductive members 101c) are directly bonded to a plurality of second interconnections (plurality of conductive members 102c) and a first nonconductive field region (surface of layer 101b at interface 102d) is directly bonded to a second nonconductive field region (surface of layer 102b at interface 102d) (see [0015], [0019-0020], [0025] and [0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the bonding between the first die and the electronic integrated circuit die of KANG to be hybrid bonding as same as the bonded structure of CHEN because the teaching of CHEN discloses the bonding between two electronic circuit die can be hybrid for directly bonding or indirectly bonding method using solder ball and molding layer and hybrid bonding would lower power consumption, improved signal integrity and enhancing thermal performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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