DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 06/06/2025. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5–8, 14, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0396271 A1 in view of Asadi et al. (US 2025/0370857 A1).
Claim 1: Regarding claim 1, ’271 teaches receiving data to be decoded. In particular, ’271 teaches reading a sense word from a memory device and temporarily storing the sense word while parity-check and error-correction operations are performed (¶48). ’271 further teaches calculating a syndrome from the data. Specifically, ’271 teaches executing a plurality of parity-check equations on corresponding subsets of the sense-word bits (¶49). Each parity-check equation produces a result indicating whether the corresponding parity-check equation is satisfied or unsatisfied (¶49). The parity-check component combines the parity-check-equation results to determine a syndrome for the sense word (¶50). Each bit of the syndrome represents the result of a corresponding parity-check equation (¶¶51–52). Additionally, ’271 teaches determining an error metric from the syndrome. Specifically, ’271 teaches determining a syndrome weight, wherein the syndrome weight represents the number of unsatisfied parity-check equations or nonzero syndrome symbols (¶56; see also ¶17). ’271 teaches comparing the error metric with a threshold. The parity-check component determines whether the syndrome weight satisfies a threshold criterion associated with a next iteration of a first decoding operation (¶57). The criterion is satisfied when the syndrome weight is greater than or equal to a corresponding threshold value and is not satisfied when the syndrome weight is below the threshold value (¶58). ’271 teaches first and second decoding circuitry. The first decoder performs an iterative bit-flip decoding operation, and the second decoder performs a Min-Sum decoding operation (¶57). The second decoding operation has higher error-correction capability than the first decoding operation but is less energy efficient (¶57; see also ¶16). ’271 explains that bit-flip decoding consumes relatively little power but has weaker correction capability, while Min-Sum decoding consumes more resources but has higher correction capability (¶¶16, 60–61). ’271 also teaches selecting between the first and second decoding operations based on the syndrome weight. When the syndrome weight satisfies the threshold criterion, the parity-check component bypasses or terminates the bit-flip decoding operation and initiates the Min-Sum decoding operation (¶59). When the syndrome weight does not satisfy the threshold criterion, the parity-check component performs the first or next iteration of the bit-flip decoding operation (¶62). Thus, ’271 teaches calculating a syndrome, determining a syndrome-weight error metric, comparing the error metric with a threshold, and selecting between first and second decoding operations based on that comparison.
However, ’271 does not expressly teach that the preliminary syndrome is calculated using a deliberately selected reduced portion H_1 of the parity-check matrix.
Asadi teaches selecting a smaller group of rows from the original ECC parity-check matrix H, with the selected subset denoted H_1, and calculating a partial checksum using the reduced group of check nodes (¶76). Asadi further teaches selecting a subset matrix from an ECC parity-check matrix and performing a partial checksum using the subset matrix to estimate bit-error rate (“BER”) (¶¶96, 102).
Asadi explains that checksum or syndrome weight is the number of nonzero syndrome bits and is correlated with the number of erroneous bits in the data (¶¶73–74). Asadi teaches that a partial checksum calculated from H_1 follows the same error trend as a full checksum and can be used to estimate raw bit-error rate (“RBER”) (¶¶80–81, 104). Asadi provides a specific example in which the original matrix H has dimensions 4352 \times 37376, while the selected subset H_1 has dimensions 256 \times 37376 and contains a single circulant layer (¶80).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the preliminary syndrome-weight calculation of ’271 so that the syndrome is calculated using a selected reduced portion H_1 of the parity-check matrix, as taught by Asadi. Asadi expressly teaches that use of H_1 reduces the memory needed to store parity-check information and reduces gate count while providing a partial checksum suitable for estimating RBER (¶76). Asadi also characterizes the resulting implementation as a gate-count-efficient syndrome calculator (¶¶88, 96, 101–102). A person of ordinary skill therefore would have had reason to use Asadi’s reduced-H_1 syndrome calculator in the threshold-controlled decoder-selection system of ’271 to reduce circuitry, storage requirements, and computational complexity while retaining an error metric representative of the error condition of the received data.
Claim 2: Regarding claim 2, ’271 teaches that when the syndrome weight satisfies the threshold criterion, the parity-check component bypasses the first decoding operation and initiates the second decoding operation (¶59). The bypass can occur before any iteration of the first decoding operation is performed. Alternatively, if the first decoding operation has already begun, the first operation can be terminated before its maximum number of iterations is reached, and the second decoding operation can then be initiated (¶59).
Claim 5: Regarding claim 5, ’271 teaches a parity-check component containing separate first and second decoders, including a bit-flip decoder and a Min-Sum decoder (¶36). The parity-check component determines which decoder to employ based on the syndrome weight (¶36). ’271 teaches syndrome-calculation circuitry that executes parity-check equations on corresponding subsets of a sense word and combines the results to determine the syndrome (¶¶49–52). It further teaches determining the syndrome weight, comparing the syndrome weight with a threshold, and selecting the first or second decoder based on the comparison (¶¶56–59, 62).
However, ’271 does not expressly teach that its preliminary syndrome circuitry calculates the syndrome using a deliberately reduced portion H_1 of the parity-check matrix.
Asadi teaches a checksum calculator containing a gate-count-efficient syndrome-calculator module (¶¶88, 101–102). The calculator receives codeword data from a NAND read buffer and receives matrix information identifying the entries of H_1 used in the partial-checksum calculation (¶88). The selected codeword data and H_1 column-entry information are supplied to AND gates, and the outputs are combined by an XOR unit to generate the partial syndrome/checksum (¶88). The results can then be totalized by a counter (¶89). Asadi additionally teaches that the checksum calculator can include a first input receiving codeword data, a second input receiving information identifying the reduced parity-check matrix, and logic configured to XOR selected codeword data to generate and totalize the checksums (¶103).
It would have been obvious to implement the preliminary syndrome circuitry of ’271 using Asadi’s reduced-H_1, gate-count-efficient syndrome calculator because Asadi teaches that such an implementation reduces matrix-storage requirements, design complexity, and gate count (¶¶76, 86, 96).
Claim 6: Regarding claim 6, ’271 teaches comparing the syndrome weight with a threshold and determining that the threshold criterion is satisfied when the syndrome weight is greater than or equal to the threshold value (¶58). In response to the higher syndrome weight satisfying the threshold criterion, the parity-check component bypasses the first decoding operation and initiates the second, higher-correction-capability decoding operation (¶¶57, 59).
Claim 7: Regarding claim 7, ’271 teaches that the threshold criterion is not satisfied when the syndrome weight is less than the corresponding threshold value (¶58). When the syndrome weight does not satisfy the criterion, the parity-check component performs the first iteration or a subsequent iteration of the first, lower-complexity bit-flip decoding operation (¶62).
Claim 8: Regarding claim 8, ’271 expressly teaches bypassing the first decoding operation and proceeding directly to the second decoding operation when the syndrome weight satisfies the applicable threshold criterion (¶59). The first decoding operation can be bypassed before any of its iterations are performed, or it can be terminated after one or more iterations and before reaching its maximum number of iterations (¶59).
Claim 14: Regarding claim 14, ’271 does not expressly teach that the preliminary syndrome circuitry lacks circuitry configured to shift bits of the data or calculated syndrome.
Asadi teaches that QC-LDPC matrices are composed of circulant submatrices or layers and that the shift values associated with the circulant submatrices used for the partial-checksum calculation can be converted to zero (¶82). Asadi expressly applies this zero-shift conversion where H_1 contains a single circulant layer or circulant row of the original matrix H (¶82). Asadi explains that a barrel shifter is conventionally used to align or correct bits and that such a barrel shifter is gate-count costly (¶86). Because the shift values for the selected H_1 matrix are set to zero, Asadi teaches that a barrel shifter is not needed to calculate the partial checksum (¶86). Asadi further describes a checksum-calculator implementation that does not require a barrel shifter and expressly states that its checksum-calculator modules need not include barrel shifters (¶¶87, 90). It would have been obvious to implement the preliminary syndrome circuitry of ’271 using Asadi’s shifter-free partial-syndrome calculator because Asadi expressly teaches that eliminating the barrel shifter substantially reduces the required gate count (¶86).
Claim 15: Regarding claim 15, ’271 teaches reading a sense word from a memory device and calculating a syndrome and syndrome weight for the sense word (¶¶48–50, 56). It further teaches comparing the syndrome weight with a threshold and selecting between first and second decoding operations (¶¶57–59, 62).
However, ’271 does not expressly teach calculating the preliminary syndrome using “a portion of a parity-check matrix and a portion of the first data corresponding to the portion of the parity-check matrix.”
Asadi teaches selecting a reduced portion H_1 from an ECC parity-check matrix H and calculating a partial checksum using H_1 (¶¶76, 96, 102). Asadi’s checksum calculator receives codeword-bit-sequence data from a NAND read buffer and receives matrix information identifying the entries of H_1 used in the partial-checksum calculation (¶88). The H_1 column-entry information identifies the circulant columns containing nonzero matrix elements, thereby selecting the corresponding codeword bits that participate in the partial syndrome calculation (¶88). The selected codeword bits and column-entry values are supplied to AND gates and combined by an XOR unit (¶88).Asadi expressly describes a first input receiving the codeword data, a second input receiving reduced-parity-check-matrix information, and logic configured to XOR selected codeword data and totalize the resulting checksums (¶103). It would have been obvious to use Asadi’s H_1 and corresponding selected-codeword-bit calculation to produce the preliminary error metric used in ’271’s decoder-selection process because Asadi teaches that the calculation estimates RBER while using reduced-complexity circuitry (¶¶76, 81, 96, 104).
Claim 18: Regarding claim 18, Asadi teaches calculating a preliminary partial syndrome using a particular selected layer having zero shift values and corresponding portions of the codeword data. Asadi teaches that H_1 can contain a single circulant layer of the original matrix H and that the shift values associated with the selected partial-checksum matrix can be converted to zero (¶82). Asadi’s disclosed example uses an H_1 consisting of a single circulant layer having a QC size of 256 (¶80). Asadi teaches supplying codeword-bit-sequence data and H_1 column-entry information to the checksum calculator (¶88). Each column-entry bit corresponds to a circulant column in H_1, and a column-entry value of one indicates that the corresponding H_1 circulant column contains nonzero matrix elements (¶88). The corresponding codeword bits and column-entry data are ANDed, and the resulting selected values are XORed to generate the partial syndrome/checksum (¶88). Asadi further explains that data from selected circulants can be processed in parallel and that the resulting error values are totalized by a counter (¶89). Asadi specifically states that its “q-copies” implementation processes only one circulant row in H_1 (¶89). It would have been obvious to use Asadi’s partial syndrome, calculated from the selected zero-shift layer and its corresponding codeword bits, as the preliminary syndrome-weight input to the decoder-selection process of ’271 because Asadi teaches that the partial checksum estimates RBER and follows the same error trend as the full checksum while requiring less hardware (¶¶76, 80–81, 86).
Claim 20: Regarding claim 20, ’271 expressly teaches that the second decoding operation has higher error-correction capability than the first decoding operation (¶57). ’271 explains that the bit-flip decoder consumes less power but has relatively weak error-correction capability, whereas the Min-Sum decoder consumes more resources but has higher error-correction capability and can correct more errors (¶16). ’271 additionally explains that Min-Sum decoding performs more extensive message calculations than bit-flip decoding, which requires fewer resources per iteration (¶61).
Claims 3, 4, and 10–13 are rejected under 35 U.S.C. §103 as being unpatentable over ’271 in view of US 2023/0396271 A1 and Asadi and further in view of Zhang et al. (US 2017/0063400 A1).
Claim 3: Regarding claim 3, ’271 teaches that the first decoding operation is an iterative bit-flip decoding operation (¶57). When the syndrome weight does not satisfy the threshold criterion, the first or next bit-flip iteration is performed (¶62). ’271 further teaches determining whether the number of performed iterations satisfies an iteration criterion by comparing an iteration counter with a maximum number of iterations (¶63). When the maximum number of iterations is reached, the first decoding operation is terminated and the second decoding operation is initiated (¶63). Zhang independently teaches that an iterative LDPC decoding process can terminate when all syndrome values are zero or when a predetermined maximum number of iterations has been performed (¶30). Zhang teaches declaring decoding failure when the maximum number of iterations has been performed and at least one syndrome remains nonzero (¶30). It would have been obvious to apply Zhang’s express decoding-failure criterion to the iterative decoder of ’271 because a remaining nonzero syndrome after the maximum number of iterations indicates that the first decoder has failed to produce a valid codeword and that stronger decoding is warranted.
Claim 4: Regarding claim 4, Asadi teaches calculating the preliminary syndrome using a selected layer of the parity-check matrix. Specifically, Asadi teaches an H_1 formed from a single circulant layer of the original parity-check matrix H (¶80). Asadi also teaches converting the shift values associated with the circulant submatrices used for the partial-checksum calculation to zero, including when H_1 contains a single layer or circulant row (¶82).Because the shift values are set to zero, Asadi teaches that a barrel shifter is not needed to calculate the partial checksum (¶86).
Zhang confirms the decoding significance of the zero numerical value. Zhang teaches that the shift amount is based on a corresponding portion of parity-check matrix H and represents the offset of a cyclically shifted identity submatrix (¶47). Zhang teaches that the shift amount may equal zero (¶47) and expressly states that when shift amount k is zero, no bit shift is performed (¶69). It would have been obvious to use Asadi’s single, zero-shift H_1 layer in the preliminary syndrome calculator applied to ’271 because Asadi teaches that setting the shift values to zero eliminates the need for a gate-count-costly barrel shifter and substantially reduces circuit complexity (¶86). Zhang confirms that a zero-valued QC-LDPC shift corresponds to performing no bit shift during decoding (¶69).
Claim 10: Regarding claim 10, Zhang teaches that a QC-LDPC parity-check matrix H consists of rows and columns of square submatrices of the same size, where each submatrix is either a zero matrix or a cyclically shifted identity matrix (¶32). Thus, the QC-LDPC matrix contains a plurality of respective bit-pattern sets represented by its zero and cyclically shifted identity submatrices. Asadi likewise teaches a QC-LDPC parity-check matrix composed of cyclic or circulant submatrices or layers of the same size (¶82).
Claim 11: Regarding claim 11, Zhang teaches that a shift amount is associated with a corresponding portion or submatrix of parity-check matrix H and that the shift amount corresponds to the numerical offset of the cyclically shifted identity submatrix (¶47). Thus, Zhang teaches a respective numerical value associated with the corresponding bit-pattern or submatrix set.
Claim 12: Regarding claim 12, Zhang teaches that each numerical shift amount is based on the corresponding portion or submatrix of parity-check matrix H (¶47). Asadi teaches selecting one or more circulant layers from the ECC parity-check matrix to form the reduced matrix H_1 (¶¶76, 80, 82, 99). In the single-layer implementation, the selected portion H_1 corresponds to one particular circulant layer or row of the original matrix H (¶¶80, 82).
Claim 13: Regarding claim 13, Asadi teaches converting the shift values associated with the nonzero circulants selected for the H_1 partial-checksum calculation to zero (¶¶82, 99, 106). Zhang expressly teaches that when the shift amount k equals zero, no bit shift is performed (¶69). Accordingly, a numerical value of zero results in zero bits being shifted.
Claims 9, 16, 17, and 19 are rejected under 35 U.S.C. §103 as being unpatentable over ’271 in view of US 2023/0396271 A1 and Asadi and further in view of Ryabinin et al. (US 2018/0159555 A1).
Claim 9: Regarding claim 9, ’271 teaches first and second decoding operations having different resource requirements and error-correction capabilities. The first operation is an iterative bit-flip operation, and the second is a Min-Sum operation having higher error-correction capability but lower energy efficiency (¶57). ’271 explains that bit-flip decoding requires fewer resources per iteration, while Min-Sum decoding requires more extensive message calculations (¶61).
Ryabinin further teaches the underlying power/correction tradeoff. Ryabinin teaches that use of a reduced-resolution processor reduces decoder power consumption, whereas a full-resolution processor provides increased correction capability at higher power consumption (¶172). Ryabinin explains that increasing the number of bits used to represent decoding messages increases decoding accuracy but also increases circuit use and power consumption (¶173). Ryabinin further teaches selectively disabling decoder components corresponding to unused message bits during reduced-resolution decoding (¶174). It would have been obvious to implement the lower-complexity and higher-complexity decoding operations of ’271 using Ryabinin’s reduced-resolution and full-resolution decoder configurations because Ryabinin teaches that selectable resolution permits power savings when lower correction capability is sufficient while retaining the ability to provide higher correction capability when needed (¶¶172–174).
Claim 16: Regarding claim 16, Ryabinin teaches processing a QC-LDPC parity-check matrix in layers. Ryabinin teaches that a decoder can process Z-tuples of bits in layers, with the number of layers depending on the ratio between decoder parallelism and QC size Z (¶92). Ryabinin further teaches a layered decoding schedule in which check nodes and the corresponding submatrix blocks are processed according to the decoder schedule (¶93). Ryabinin teaches storing address and shift values associated with the QC-LDPC matrix blocks at the original LDPC parallelism (¶93). Ryabinin also teaches that cyclic shift value s may have any integer value in the range from zero through Z-1 (¶77).
Claim 17: Regarding claim 17, Asadi teaches that the selected portion H_1 can correspond to a particular single layer or circulant row of the original parity-check matrix H (¶¶80, 82).
Asadi further teaches converting the shift values associated with the selected nonzero circulants to zero before performing the partial-checksum calculation (¶¶82, 99, 106). Ryabinin teaches an architecture in which address and shift values associated with QC-LDPC matrix blocks are stored for use during layered decoding (¶93). Ryabinin also establishes that an associated shift value may be zero because the shift value s can be any integer in the range 0 through Z-1 (¶77). It would have been obvious to store zero shift values for the circulants of Asadi’s selected H_1 layer in Ryabinin’s stored-shift-value architecture because Asadi teaches deliberately converting those values to zero to simplify the partial-checksum calculation and reduce the required storage and shifting circuitry (¶¶82, 86).
Claim 19: Regarding claim 19, ’271 teaches that, after the preliminary syndrome-weight determination, the selected decoding circuitry performs an actual LDPC decoding operation. The available operations include iterative bit-flip decoding and Min-Sum decoding (¶¶57, 59–61). Ryabinin teaches performing QC-LDPC decoding using a plurality of layers. Ryabinin teaches that a decoder processes Z-tuples of bits in layers (¶92) and describes a layered schedule for processing check nodes and corresponding QC-LDPC submatrix blocks (¶93). Asadi teaches that the preliminary checksum calculation may use only a reduced subset H_1, including a single circulant layer, rather than all rows of the original parity-check matrix H (¶¶76, 80, 82). It would have been obvious to use Asadi’s reduced H_1 only for the preliminary error estimation while using the plurality of QC-LDPC layers during the actual decoding operation, as taught by Ryabinin. The reduced calculation provides a lower-complexity preliminary estimate, while the full layered decoder retains the parity-check information used to perform error correction.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 9/2/2026
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