DETAILED ACTION
This action is responsive to 06/09/2025.
Claims 1-6 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US Pub. 2019/0172843), hereinafter Yoshida, in view of Ito (US Pub. 2023/0082769).
Regarding claim 1, Yoshida discloses a drive circuit including a plurality of stages (see figs. 7 and 19-shift register stages SR1 to SRi) and configured to supply a drive signal to a group of scanning signal lines (i.e., supply gate output signals (Gout1 to Gouti) to corresponding gate bus lines GL1-GLi-see figs. 1, 7, and [0060]) in response to an input of a clock signal (clock signal CKA-see figs. 7, 19, and [0096]), the drive circuit comprising: a plurality of unit circuits, each of the plurality of unit circuits constituting one stage of the plurality of stages (a shift register (SR1-Sri) 240-see figs. 7 and 19) and outputting the drive signal to a scanning signal line of the group of scanning signal lines (i.e., gate output signals Gout1-Gouti)-see fig. 7), wherein each of the plurality of unit circuits includes a node (node netA-see fig. 19), a first transistor configured to output the drive signal to the scanning signal line (TFT-F, see fig. 19), the first transistor including a gate electrode connected to the node (gate of TFT-F is connected to netA-see fig. 19), a source electrode being applied with the clock signal (clock signal CKA is applied to source electrode of TFT-F at 116-see fig. 19), and a drain electrode connected to the scanning signal line (drain of TFT-F is connected to output node (i.e., to a corresponding scan signal line-see fig. 19), a second transistor configured to receive a set signal for each of the plurality of unit circuits (TFT-B receives a set signal (S) at input 111-see fig. 19), the second transistor including a gate electrode configured to receive the set signal (111 is gate electrode of TFT-B, see fig. 19) and a drain electrode connected to the node (drain of TFT-B is connected to netA-see fig. 19), and a third transistor configured to receive a reset signal for each of the plurality of unit circuits (TFT-A (third transistor) receives a reset signal (CLR)-see fig. 19), the third transistor including a gate electrode configured to receive the reset signal (i.e., gate of TFT-A (113) receives the reset signal CLR) and a drain electrode connected to the node (i.e., drain of TFT-A is coupled to netA-see fig. 19), at least one of the second transistor and the third transistor includes a first semiconductor portion connected to the drain electrode of at least one of the second transistor and the third transistor, and a second semiconductor portion connected to the source electrode of at least one of the second transistor and the third transistor (see fig. 19-TFT-A and TFT-B each comprises two series-connected transistors).
Yoshida does not appear to expressly disclose the gate electrode of at least one of the second transistor and the third transistor includes a first gate portion overlapping the first semiconductor portion, and a second gate portion overlapping the second semiconductor portion, at least one of the second transistor and the third transistor includes a first channel being a portion of the first semiconductor portion overlapping with the first gate portion, and a second channel being a portion of the second semiconductor portion overlapping with the second gate portion, and in a plan view, in a case where a direction from the drain electrode to the source electrode is defined as a first direction and a direction orthogonal to the first direction is defined as a second direction, a length of the second channel in the first direction is longer than a length of the first channel in the first direction, or a length of the second channel in the second direction is shorter than a length of the first channel in the second direction, or mobility of electrons or holes in the second semiconductor portion is lower than mobility of electrons or holes in the first semiconductor portion.
Ito is relied upon to teach (see Ito (US Pub. 2023/0082769-see, for example, figs. 4-5 and [0067], which illustrates a drive transistor having a gate electrode G1 that overlaps a semiconductor layer 33, the gate electrode G1 having a first gate region G1d and a second gate region G1s, both overlapping the semiconductor layer 33), at least one of the second transistor and the third transistor includes a first channel being a portion of the first semiconductor portion overlapping with the first gate portion, and a second channel being a portion of the second semiconductor portion overlapping with the second gate portion (i.e., overlapping portions of G1d (33chd) and G1s (33chs)-figs. 4-5 and [0070]), and in a plan view, in a case where a direction from the drain electrode to the source electrode is defined as a first direction and a direction orthogonal to the first direction is defined as a second direction, a length of the second channel in the first direction is longer than a length of the first channel in the first direction (i.e., a length GD of the first channel region 33chd in the channel direction X1 is shorter than a length GS of the second channel region 33chs in the channel direction X1-see figs. 4-5 and [0063] and [0068]), or a length of the second channel in the second direction is shorter than a length of the first channel in the second direction, or mobility of electrons or holes in the second semiconductor portion is lower than mobility of electrons or holes in the first semiconductor portion.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the dual gate transistor structure of Ito with the invention of Yoshida in order to provide a display device in which the display device suppresses a current change with respect to a voltage change of a drive transistor, and suppresses a shift amount of a threshold voltage of the drive transistor (see [0007]).
Regarding claim 2, Ito is further relied upon to teach wherein a length of the second gate portion in the first direction is longer than a length of the first gate portion in the first direction, causing the length of the second channel in the first direction to be longer than the length of the first channel in the first direction (see figs. 4-5 with description in [0063], wherein, channel 33chs is longer than channel 33chd).
Regarding claim 5, Yoshida discloses an active matrix substrate comprising: the drive circuit according to claim 1; and a substrate on which the drive circuit is located (see [0030]).
Regarding claim 6, Yoshida discloses a display device comprising: the drive circuit according to claim 1 (see fig. 1 and [0030]-a liquid crystal display device); a substrate on which the drive circuit is located; and a counter substrate located facing the substrate (see [0030]-a liquid crystal device having a matrix substrate and a counter substrate).
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Ito, and further in view of Sung et al. (US Patent 10,170,484).
Regarding claim 3, Yoshida in view of Ito does not appear to expressly disclose wherein a length of the second semiconductor portion in the second direction is shorter than a length of the first semiconductor portion in the second direction, causing the length of the second channel in the second direction to be shorter than the length of the first channel in the second direction.
Sung teaches that in multi-gate transistors (e.g., dual-gate FETs), different effective channel widths can be achieved by using different numbers of semiconductor fins within different FETs and/or by using semiconductor fins having different heights within the different FETs (see [col. 4, ll. 37-54]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Sung with the inventions Yoshida and Ito, by using semiconductor fins having different heights to achieve different channel widths, as taught by Sung, in order to achieve optimal circuit performance (see [col. 4, ll. 37-41]).
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Ito, and further in view of Kikuchi et al. (US Pub. 2022/0406942), hereinafter Kikuchi.
Regarding claim 4, Yoshida in view of Ito teaches wherein at least one of the second transistor and the third transistor includes a first semiconductor layer including the first semiconductor portion formed in the first semiconductor layer, and a second semiconductor layer including the second semiconductor portion formed in the second semiconductor layer and being a layer different from the first semiconductor layer (see Ito, for example, figs. 14 and 15 with description in [0136]-[0146], wherein semiconductor layer 33 includes a first semiconductor layer 33D1 and a second semiconductor layer 33S1 separated from the first semiconductor layer 33D1, wherein, 33D1 includes the first channel 33chd overlapping the first gate region G1d, and 33S1 includes the channel region 33chs overlapping the second region G1s in the first gate electrode G1).
Yoshida in view of Ito does not appear to expressly teach and the mobility of electrons or holes in the second semiconductor portion is lower than the mobility of electrons or holes in the first semiconductor portion.
Kikuchi, in for example, [0021], teaches an oxide semiconductor TFT having layers with different mobilities.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kikuchi with the inventions of Yoshida and Ito by using thin-film transistors having semiconductor layer portions with different mobilities, as taught by Kikuchi, in order to provide a display device including a thin film transistor that can reduce a variation in characteristics or can suppress a decrease in reliability (see [0063]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
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/SARDIS F AZONGHA/ Primary Examiner, Art Unit 2627
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