DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, 13, 15-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US Pub 2006/0227081) in view of PARK et al (US Pub 2021/0183283) and Liu et al (US Pub 2007/0126682).
With respect to claim 1, Joo discloses a display device (par 0010; discloses present invention also provides a display device having the above display panel) comprising: a first scan line configured to receive a first scan signal; a second scan line configured to receive a second scan signal (fig. 7; gate driving section 270; par 0093; discloses Gate driving section 270 generates gate signals G1, . . . , Gn based on the third control signal received over line 216 from timing control section 210. Gate signals G1, . . . , Gn have waveforms shown in FIGS. 5A, 5B, 6A and 6B); a data line configured to receive a first data voltage and a second data voltage (fig. 7; data driving section 250; par 0091; discloses Data driving section 250 converts first data signal received over line 218 from timing control section 210 into analog second data signals D1 . . . Dm based on reference gamma voltage and outputs the second data signals D1 . . . Dm to data bus lines); a first pixel electrically connected to the first scan line and the data line (fig. 1; discloses pixel P2 connected to the first scan line GLn and data line DLm); and a second pixel electrically connected to the first scan line, the second scan line, and the data line, (fig. 1; discloses pixel P1 connected to first scan line GLn, second scan line GL(n+1) and the data line DLm) wherein the first pixel includes a first light emitting element, a first driving transistor connected to the first light emitting element, and a first switching transistor connected between a gate of the first driving transistor and the data line, (fig.1; discloses pixel P2 includes a first light emitting element EL2, a first driving transistor QD2 connected to the light emitting element EL2, a first switching transistor QS22 connected between a gate of the driving transistor DQ2 and the data line DLm via transistor QS21) wherein the second pixel includes a second light emitting element, a second driving transistor connected to the second light emitting element, and a second switching transistor connected between a gate of the second driving transistor and the data line, (fig. 1; discloses pixel P1 includes a second light emitting element EL1, a second driving transistor QD1 connected to the light emitting element EL1, a second switching transistor QS12 connected to the gate electrode of the driving transistor QD1 and the data line DLm via transistor QS11);
Joo doesn’t expressly disclose wherein the first switching transistor and the second switching transistor, which are included in different pixels and are connected between the data line and the gate of the driving transistor of respective pixels, are configured such that one of the first switching transistor and the second switching transistor is an N-type transistor, and the other one thereof is a P-type transistor;
In the same field of endeavor, Park discloses a display device comprising plurality of pixels (see fig. 1; pixels P); Park discloses wherein the switching transistors in a pixel circuit may be an N-type transistor, a P-type transistor or mixed (par 0076; discloses Each pixel P includes an OLED which is a light emitting element, a driving thin film transistor DT which is a driving element, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. The TFTs constituting the pixel P may be implemented in p-type, or implemented in a n-type, or implemented in a hybrid type in which p-type and n-type are mixed);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo incorporate the teachings of Park to form the switching transistors using only the P-type transistors, or using only the N-type transistor or using the combination of P-type and N-type transistor in order to control the light emitting element of the pixel accurately using the data voltage to emit the light;
Joo as modified by Park don’t expressly disclose wherein the first switching transistor and the second switching transistor, which are included in different pixels and are configured such that one of the first switching transistor and the second switching transistor is an N-type transistor, and the other one thereof is a P-type transistor;
In the same field of endeavor, Liu discloses a display device comprising shared gate lines and data lines (see abstract); Liu discloses wherein the first switching transistor and the second switching transistor, which are included in different pixels and are configured such that one of the first switching transistor and the second switching transistor is an N-type transistor, and the other one thereof is a P-type transistor (par 0021; discloses The first pixel unit 208 includes a P-type thin film transistor 203 (i.e. first switching transistor), a first storage capacitor 205, a first pixel electrode 206, and a common electrode 207; par 0022; discloses The second pixel unit 218 includes an N-type thin film transistor 213 (i.e. second switching transistor), a second storage capacitor 215, a second pixel electrode 216, and the common electrode 207. See par 0027-0028 as well);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park to incorporate the teachings of Liu to form the switching transistor of first pixel to be P-type while form the switching transistor or second pixel to be N-type in order to allow the two adjacent pixel to share the same gate lines and data lines while activating the two switching transistor of two different pixels at different times. The modification would reduce the number of scan lines required on the display panel.
With respect to claim 2, Joo as modified by Park and Liu discloses wherein a gate of the first switching transistor is connected to the first scan line, and an operation of the first switching transistor is controlled by the first scan signal, (Joo; fig. 1; discloses a gate electrode of the transistor QS22 is connected to the scan line GLn and controlled by it) and wherein a gate of the second switching transistor is connected to the second scan line, and an operation of the second switching transistor is controlled by the second scan signal (Joo; fig. 1; discloses a gate electrode of the transistor QS12 is connected to the scan line GL(n+1) and controlled by it).
With respect to claim 3, Joo as modified by Park and Liu discloses wherein the second pixel further includes a third switching transistor (Joo; fig. 1; discloses pixel P1 includes transistor QS11), and wherein a gate of the third switching transistor is connected to the first scan line, and an operation of the third switching transistor is controlled by the first scan signal (Joo; fig. 1; discloses transistor QS11 connected between the gate electrode of the driving transistor QD1 and the data line DLm and gate electrode is connected to the first scan line GLn);
Joo as modified by Park and Liu don’t expressly disclose third switching transistor connected between the gate of the second driving transistor and the second switching transistor;
Joo discloses second switching transistor QS12 and third switching transistor QS11 are connected in series between the data line DLm and the gate of the driving transistor QD1 (see fig. 1; transistor QS12, QS11 and QD1);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to switch the location of transistors QS11 and QS12 and still achieve the same predictable result of transmitting the data signal to the gate electrode of the driving transistor QD1 when both transistor QS11 and QS12 are turned on.
With respect to claim 4, Joo as modified by Park and Liu discloses wherein the first switching transistor is an N-type transistor, the second switching transistor is a P-type transistor, (Liu; par 0021; discloses The first pixel unit 208 includes a P-type thin film transistor 203 (i.e. first switching transistor), a first storage capacitor 205, a first pixel electrode 206, and a common electrode 207; par 0022; discloses The second pixel unit 218 includes an N-type thin film transistor 213 (i.e. second switching transistor), a second storage capacitor 215, a second pixel electrode 216, and the common electrode 207);
Joo as modified by Park and Liu don’t expressly discloses the third switching transistor is an N-type transistor;
Park further discloses wherein the first switching transistor is an N-type transistor, the second switching transistor is a P-type transistor, and the third switching transistor is an N-type transistor; (par 0076; discloses Each pixel P includes an OLED which is a light emitting element, a driving thin film transistor DT which is a driving element, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. The TFTs constituting the pixel P may be implemented in p-type, or implemented in a n-type, or implemented in a hybrid type in which p-type and n-type are mixed);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu incorporate the teachings of Park to form the switching transistors using only the P-type transistors, or using only the N-type transistor or using the combination of P-type and N-type transistor in order to control the light emitting element of the pixel accurately using the data voltage to emit the light.
With respect to claim 6, Joo as modified by Park and Liu discloses wherein the second pixel further includes a third switching transistor connected between the second switching transistor and the data line, (Joo; fig. 1; discloses pixel P1 includes transistor QS11 connected between the second switching transistor QS12 and the data line DLm) and wherein a gate of the third switching transistor is connected to the first scan line, and an operation of the third switching transistor is controlled by the first scan signal (Joo; fig. 1; discloses the gate electrode of the transistor QS11 is connected to the first scan line GLn and controlled by it).
With respect to claim 7, Joo as modified by Park and Liu don’t expressly disclose wherein the first switching transistor is electrically connected to a connection node between the second switching transistor and the third switching transistor, and the first switching transistor is electrically connected to the data line through the third switching transistor;
Joo discloses, in one embodiment, the first switching transistor connected to the data line directly (fig. 4; discloses transistor QS2 directly connected to data line DLm); Joo further discloses in different embodiment, the first switching transistor connected to data line via an intermediary transistor (fig. 1; discloses transistor QS22 connected to data line DLm via transistor QS21); Joo further discloses transistor QS12 connected to data line DLm via transistor QS11 (fig. 1; discloses transistor QS12 connected to data line via transistor QS11);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to connect the transistor QS22 to data line DLm via transistor QS12 and still achieve the same predictable result of transmitting the data signal to the gate electrode of the driving transistor such that light emitting element may emit light based on the data signal.
With respect to claim 13, Joo as modified by PARK and Liu wherein a first part of the first scan signal in a first level section overlaps a second part of the second scan signal in a second level section (Joo; fig. 5A-5B; discloses a part of the first scan signal Gn overlaps with a part of the second scan signal Gn+1).
With respect to claim 15, Joo discloses an electronic device includes a display device for displaying an image (par 0010; discloses present invention also provides a display device having the above display panel), the display device comprising: a first pixel including a first driving transistor and a first switching transistor (fig. 1; first pixel P2 comprising a first driving transistor QD2, a first switching transistor QS22); a second pixel including a second driving transistor and a second switching transistor (fig. 1; second pixel P1 comprising a second driving transistor QD1 and a second switching transistor QS12); a first scan line configured to receive a first scan signal (fig. 1; first scan line GLn); a second scan line configured to receive a second scan signal (fig. 1; second scan line GL(n+1)); and a data line electrically connected to the first pixel and the second pixel (fig. 1; data line DLm connected to first pixel P2 and second pixel P1), wherein a gate of the first switching transistor is connected to the first scan line, and an operation of the first switching transistor is controlled by the first scan signal, (fig. 1; discloses gate electrode of the first switching transistor QS22 is connected to first scan line GLn and controlled by it) wherein a gate of the second switching transistor is connected to the second scan line, and an operation of the second switching transistor is controlled by the second scan signal (fig. 1; discloses a gate electrode of the transistor QS12 s connected to second scan line GL(n+1) and controlled by it);
Joo doesn’t expressly disclose wherein the first switching transistor and the second switching transistor, which are included in different pixels and are connected between the data line and the gate of the driving transistor of respective pixels, are configured such that one of the first switching transistor and the second switching transistor is an N-type transistor, and the other one thereof is a P-type transistor;
In the same field of endeavor, Park discloses a display device comprising plurality of pixels (see fig. 1; pixels P); Park discloses wherein the switching transistors in a pixel circuit may be an N-type transistor, a P-type transistor or mixed (par 0076; discloses Each pixel P includes an OLED which is a light emitting element, a driving thin film transistor DT which is a driving element, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. The TFTs constituting the pixel P may be implemented in p-type, or implemented in a n-type, or implemented in a hybrid type in which p-type and n-type are mixed);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo incorporate the teachings of Park to form the switching transistors using only the P-type transistors, or using only the N-type transistor or using the combination of P-type and N-type transistor in order to control the light emitting element of the pixel accurately using the data voltage to emit the light;
Joo as modified by Park don’t expressly disclose wherein the first switching transistor and the second switching transistor, which are included in different pixels and are configured such that one of the first switching transistor and the second switching transistor is an N-type transistor, and the other one thereof is a P-type transistor;
In the same field of endeavor, Liu discloses a display device comprising shared gate lines and data lines (see abstract); Liu discloses wherein the first switching transistor and the second switching transistor, which are included in different pixels and are configured such that one of the first switching transistor and the second switching transistor is an N-type transistor, and the other one thereof is a P-type transistor (par 0021; discloses The first pixel unit 208 includes a P-type thin film transistor 203 (i.e. first switching transistor), a first storage capacitor 205, a first pixel electrode 206, and a common electrode 207; par 0022; discloses The second pixel unit 218 includes an N-type thin film transistor 213 (i.e. second switching transistor), a second storage capacitor 215, a second pixel electrode 216, and the common electrode 207. See par 0027-0028 as well);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park to incorporate the teachings of Liu to form the switching transistor of first pixel to be P-type while form the switching transistor or second pixel to be N-type in order to allow the two adjacent pixel to share the same gate lines and data lines while activating the two switching transistor of two different pixels at different times. The modification would reduce the number of scan lines required on the display panel.
With respect to claim 16, Joo as modified by Park and Liu discloses wherein the second pixel further includes a third switching transistor (Joo; fig. 1; discloses pixel P1 includes transistor QS11), and wherein a gate of the third switching transistor is connected to the first scan line, and an operation of the third switching transistor is controlled by the first scan signal (Joo; fig. 1; discloses transistor QS11 connected between the gate electrode of the driving transistor QD1 and the data line DLm and gate electrode is connected to the first scan line GLn);
Joo as modified by Park and Liu don’t expressly disclose third switching transistor connected between the gate of the second driving transistor and the second switching transistor;
Joo discloses second switching transistor QS12 and third switching transistor QS11 are connected in series between the data line DLm and the gate of the driving transistor QD1 (see fig. 1; transistor QS12, QS11 and QD1);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to switch the location of transistors QS11 and QS12 and still achieve the same predictable result of transmitting the data signal to the gate electrode of the driving transistor QD1 when both transistor QS11 and QS12 are turned on.
With respect to claim 18, Joo as modified by Park and Liu discloses wherein the second pixel further includes a third switching transistor connected between the second switching transistor and the data line, (Joo; fig. 1; discloses pixel P1 includes transistor QS11 connected between the second switching transistor QS12 and the data line DLm) and wherein a gate of the third switching transistor is connected to the first scan line, and an operation of the third switching transistor is controlled by the first scan signal (Joo; fig. 1; discloses the gate electrode of the transistor QS11 is connected to the first scan line GLn and controlled by it).
With respect to claim 19, Joo as modified by Park and Liu don’t expressly disclose wherein the first switching transistor is electrically connected to a connection node between the second switching transistor and the third switching transistor, and the first switching transistor is electrically connected to the data line through the third switching transistor;
Joo discloses, in one embodiment, the first switching transistor connected to the data line directly (fig. 4; discloses transistor QS2 directly connected to data line DLm); Joo further discloses in different embodiment, the first switching transistor connected to data line via an intermediary transistor (fig. 1; discloses transistor QS22 connected to data line DLm via transistor QS21); Joo further discloses transistor QS12 connected to data line DLm via transistor QS11 (fig. 1; discloses transistor QS12 connected to data line via transistor QS11);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to connect the transistor QS22 to data line DLm via transistor QS12 and still achieve the same predictable result of transmitting the data signal to the gate electrode of the driving transistor such that light emitting element may emit light based on the data signal.
With respect to claim 20, Joo as modified by PARK and Liu wherein a first part of the first scan signal in a first level section overlaps a second part of the second scan signal in a second level section (Joo; fig. 5A-5B; discloses a part of the first scan signal Gn overlaps with a part of the second scan signal Gn+1).
Claim(s) 5, 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US Pub 2006/0227081) in view of PARK et al (US Pub 2021/0183283), Liu et al (US Pub 2007/0126682) and Shih et al (US Pub 2004/0056604).
With respect to claim 5, Joo as modified by Park and Liu discloses wherein the first pixel further includes a fourth switching transistor connected between the data line and the first switching transistor, (Joo; fig. 1; discloses pixel P2 includes a transistor QS21 connected between the data line DLm and the first switching transistor QS22);
Joo as modified by Park and Liu don’t expressly disclose wherein a gate of the fourth switching transistor is connected to the second scan line, and an operation of the fourth switching transistor is controlled by the second scan signal;
In the same field of endeavor, Shih discloses pixel circuit for a display device (see abstract); Shih discloses wherein the first pixel further includes a fourth switching transistor connected between the data line and the first switching transistor (fig. 3; transistor T31 connected between transistor T33 and the data line); wherein a gate of the fourth switching transistor is connected to the second scan line, and an operation of the fourth switching transistor is controlled by the second scan signal (fig. 3; discloses transistor T31 is controlled via line SCAN1, where transistor T33 is controlled via line SCAN2);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to incorporate the teachings of Shih to control first and fourth switching transistors using different scan signal in order to independently control each switching transistor separately while still achieving the same predictable result of supplying data signal to the driving transistor.
With respect to claim 8, Joo as modified by Park and Liu discloses wherein the first pixel further includes a fourth switching transistor connected between the first switching transistor and a first node, (Joo; fig. 1; transistor QS21 connected between the first switching transistor QS22 and a first node i.e. DLm);
Joo as modified by Park and Liu discloses wherein a gate of the fourth switching transistor is connected to the second scan line, and an operation of the fourth switching transistor is controlled by the second scan signal;
In the same field of endeavor, Shih discloses pixel circuit for a display device (see abstract); Shih discloses wherein the first pixel further includes a the first switching transistor and a first node (fig. 3; transistor T31 connected between transistor T33 and the data line); wherein a gate of the fourth switching transistor is connected to the second scan line, and an operation of the fourth switching transistor is controlled by the second scan signal (fig. 3; discloses transistor T31 is controlled via line SCAN1, where transistor T33 is controlled via line SCAN2);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to incorporate the teachings of Shih to control first and fourth switching transistors using different scan signal in order to independently control each switching transistor separately while still achieving the same predictable result of supplying data signal to the driving transistor.
With respect to claim 17, Joo as modified by Park and Liu discloses wherein the first pixel further includes a fourth switching transistor connected between the data line and the first switching transistor, (Joo; fig. 1; discloses pixel P2 includes a transistor QS21 connected between the data line DLm and the first switching transistor QS22);
Joo as modified by Park and Liu don’t expressly disclose wherein a gate of the fourth switching transistor is connected to the second scan line, and an operation of the fourth switching transistor is controlled by the second scan signal;
In the same field of endeavor, Shih discloses pixel circuit for a display device (see abstract); Shih discloses wherein the first pixel further includes a fourth switching transistor connected between the data line and the first switching transistor (fig. 3; transistor T31 connected between transistor T33 and the data line); wherein a gate of the fourth switching transistor is connected to the second scan line, and an operation of the fourth switching transistor is controlled by the second scan signal (fig. 3; discloses transistor T31 is controlled via line SCAN1, where transistor T33 is controlled via line SCAN2);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by Park and Liu to incorporate the teachings of Shih to control first and fourth switching transistors using different scan signal in order to independently control each switching transistor separately while still achieving the same predictable result of supplying data signal to the driving transistor.
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US Pub 2006/0227081) in view of PARK et al (US Pub 2021/0183283), Liu et al (US Pub 2007/0126682) and KIM et al (US Pub 2021/0201816).
With respect to claim 9, Joo as modified by PARK and Liu don’t expressly disclose wherein the first pixel further includes a first initialization transistor connected to the first light emitting element, and the second pixel further includes a second initialization transistor connected to the second light emitting element, and wherein gates of the first initialization transistor and the second initialization transistor are connected to the first scan line, and operations of the first initialization transistor and the second initialization transistor are controlled by the first scan signal;
In the same field of endeavor, KIM discloses a display device comprising plurality of pixels (see fig. 1; pixels P); KIM discloses wherein the first pixel further includes a first initialization transistor connected to the first light emitting element, (fig. 4; pixels P1 includes a first initialization transistor Tsw2 connected to the light emitting element ELD) and the second pixel further includes a second initialization transistor connected to the second light emitting element, (fig. 4; pixels P2 includes a second initialization transistor Tsw2 connected to the light emitting element ELD) and wherein gates of the first initialization transistor and the second initialization transistor are connected to the first scan line, and operations of the first initialization transistor and the second initialization transistor are controlled by the first scan signal (fig. 4; discloses first initialization transistor and second initialization transistor Tsw2 are connected to same scan line SS(n) );
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by PARK and Liu to incorporate the teachings of KIM to include an initialization transistor connected to the light emitting element of each pixel in order to reset or initialize the anode terminal of the light emitting element such that correct light is emitted by the light emitting pixel after each frame.
With respect to claim 10, Joo as modified by PARK and Liu don’t expressly disclose wherein the first driving transistor, the second driving transistor, the first initialization transistor, and the second initialization transistor are N-type transistors;
Park further discloses wherein the first driving transistor, the second driving transistor, the first initialization transistor, and the second initialization transistor are N-type transistors (par 0076; discloses Each pixel P includes an OLED which is a light emitting element, a driving thin film transistor DT which is a driving element, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. The TFTs constituting the pixel P may be implemented in p-type, or implemented in a n-type, or implemented in a hybrid type in which p-type and n-type are mixed);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by PARK and Liu incorporate the teachings of Park to form the transistors using only the P-type transistors, or using only the N-type transistor or using the combination of P-type and N-type transistor in order to control the light emitting element of the pixel accurately using the data voltage to emit the light.
With respect to claim 11, Joo as modified by PARK and Liu don’t expressly disclose wherein the first driving transistor and the second driving transistor are P-type transistors, and the first initialization transistor and the second initialization transistor are N-type transistors;
Park further discloses wherein the first driving transistor and the second driving transistor are P-type transistors, and the first initialization transistor and the second initialization transistor are N-type transistors; (par 0076; discloses Each pixel P includes an OLED which is a light emitting element, a driving thin film transistor DT which is a driving element, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. The TFTs constituting the pixel P may be implemented in p-type, or implemented in a n-type, or implemented in a hybrid type in which p-type and n-type are mixed);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by PARK and Liu incorporate the teachings of Park to form the transistors using only the P-type transistors, or using only the N-type transistor or using the combination of P-type and N-type transistor in order to control the light emitting element of the pixel accurately using the data voltage to emit the light.
With respect to claim 12, Joo as modified by PARK and Liu don’t expressly disclose wherein the first driving transistor, the second driving transistor, the first initialization transistor, and the second initialization transistor are P-type transistors;
Park further discloses wherein the first driving transistor, the second driving transistor, the first initialization transistor, and the second initialization transistor are P-type transistors; (par 0076; discloses Each pixel P includes an OLED which is a light emitting element, a driving thin film transistor DT which is a driving element, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. The TFTs constituting the pixel P may be implemented in p-type, or implemented in a n-type, or implemented in a hybrid type in which p-type and n-type are mixed);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by PARK and Liu incorporate the teachings of Park to form the transistors using only the P-type transistors, or using only the N-type transistor or using the combination of P-type and N-type transistor in order to control the light emitting element of the pixel accurately using the data voltage to emit the light.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US Pub 2006/0227081) in view of PARK et al (US Pub 2021/0183283), Liu et al (US Pub 2007/0126682) and PARK et al (US Pub 2018/0083078) referred to as PARK078.
With respect to claim 14, Joo as modified by PARK and Liu discloses wherein a length of each of the first part and the second part is greater than or equal to 0.5 horizontal periods and less than 1 horizontal period (Joo; fig. 8A-8D; discloses a length of the first part and the second part is T1 which is at least half of the horizontal period);
Joo as modified by PARK and Liu discloses wherein a length of each of the first level section and the second level section is greater than or equal to 1.5 horizontal periods and less than 2 horizontal periods;
In the same field of endeavor, PARK078 discloses a display device and driving method (see abstract); PARK078 discloses wherein a length of each of the first level section and the second level section is greater than or equal to 1.5 horizontal periods and less than 2 horizontal periods (fig. 6; discloses the length of the first level of the scan signals is greater than 1.5 horizontal periods and less than 2 horizontal periods);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Joo as modified by PARK and Liu to incorporate the teachings of PARK078 to increase the length of first level of scan signal to larger than 1 horizontal periods in order to provide data to the pixel for sufficient duration such that data is accurately provided to each pixel when light is correctly emitted.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the arguments do not apply to new reference being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUJIT SHAH/Examiner, Art Unit 2624
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