DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 4, 13, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, and 19 of U.S. Patent No. 12436815. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by the patented claims as seen in the mapping below.
Instant Application
12436915
1. A method of operating a cost estimation tool for placing and routing a logical edge onto a reconfigurable processor, comprising: receiving an operation unit graph comprising the logical edge between a logical producer unit and a logical consumer unit; receiving a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor; determining an upper bandwidth limit of the logical edge; determining a scaling factor of a realized bandwidth; determining an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determining a congestion estimation of the physical link comprising determining all logical edges of the operation unit graph that are assigned to use the physical link; and determining a realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link.
1. A method of operating a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor, comprising: receiving the operation unit graph comprising the logical producer unit, the logical consumer unit, and the logical edge; determining an upper output bandwidth limit of the logical producer unit, an upper input bandwidth limit of the logical consumer unit, and an upper bandwidth limit of the logical edge based on the upper output bandwidth limit and the upper input bandwidth limit; determining a scaling factor of a realized bandwidth; receiving a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit; determining an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determining a congestion estimation of the physical link; and determining the realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link; and providing the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool.
4. The method of claim 1, further comprising: providing the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool.
1. A method of operating a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor, comprising: receiving the operation unit graph comprising the logical producer unit, the logical consumer unit, and the logical edge; determining an upper output bandwidth limit of the logical producer unit, an upper input bandwidth limit of the logical consumer unit, and an upper bandwidth limit of the logical edge based on the upper output bandwidth limit and the upper input bandwidth limit; determining a scaling factor of a realized bandwidth; receiving a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit; determining an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determining a congestion estimation of the physical link; and determining the realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link; and providing the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool.
13. A system, comprising: a cost estimation tool for placing and routing a logical edge onto a reconfigurable processor, wherein the cost estimation tool is configured to: receive an operation unit graph comprising the logical edge between a logical producer unit and a logical consumer unit; receive a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor; determine an upper bandwidth limit of the logical edge; determine a scaling factor of a realized bandwidth; determine an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determine all logical edges of the operation unit graph that are assigned to use the physical link; determine a sum of realized average bandwidths of all the logical edges that are assigned to use the physical link to determine a congestion estimation of the physical link; and determine a realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link.
12 A system, comprising: a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor, wherein the cost estimation tool is configured to: receive the operation unit graph comprising the logical producer unit, the logical consumer unit, and the logical edge; determine an upper output bandwidth limit of the logical producer unit, an upper input bandwidth limit of the logical consumer unit, and an upper bandwidth limit of the logical edge based on the upper output bandwidth limit and the upper input bandwidth limit; determine a scaling factor of a realized bandwidth; receive a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit; determine an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determine a congestion estimation of the physical link; determine the realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link; and provide the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool.
20. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a cost estimation tool for placing and routing a logical edge onto a reconfigurable processor, the instructions comprising: receiving an operation unit graph comprising the logical edge between a logical producer unit and a logical consumer unit; receiving a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor; determining an upper bandwidth limit of the logical edge; determining a scaling factor of a realized bandwidth; determining an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determining a congestion estimation of the physical link comprising determining all logical edges of the operation unit graph that are assigned to use the physical link; and determining a realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link.
19 A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor, the instructions comprising: receiving the operation unit graph comprising the logical producer unit, the logical consumer unit, and the logical edge; determining an upper output bandwidth limit of the logical producer unit, an upper input bandwidth limit of the logical consumer unit, and an upper bandwidth limit of the logical edge based on the upper output bandwidth limit and the upper input bandwidth limit; determining a scaling factor of a realized bandwidth; receiving a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit; determining an end-to-end bandwidth between the physical producer unit and the physical consumer unit; determining a congestion estimation of the physical link; determining the realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link providing the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 – 5, 9, 11 – 14, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable Kumar et al. (US Publication Number 2015/0036536, hereinafter “Kumar”) in view of Schreiber et al. (US Patent Number 6,438,747, hereinafter “Shreiber”) further in view of Barkey et al. (US Patent Number 6,044,406, hereinafter “Barkey”).
5. As per claims 1, 13, and 20, Kumar teaches a method, system, and non-transitory computer-readable storage medium comprising: a cost estimation tool (1011 having 1011-4, figure 10, paragraphs 110 – 112) for placing and routing a logical edge (system traffic flow, figures 9a…d, paragraph 106) onto a processor (1010, figure 10, paragraph 108 and 110), wherein the cost estimation tool is configured to: receive an operation unit graph (connectivity spec of host and system traffic flows therein, figures 4a, 5a, and 9a) comprising the logical edge between a logical producer unit (source host, figure 9a, paragraphs 90 - 92) and a logical consumer unit (destination host, figure 9a, paragraphs 90 – 92, traffic flow with optimal routes identified at 801, figure 8, and connectivity, figure 5a, paragraphs 51, 86, and 106); receive a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link (NoC link/channel between routers figures 5b…d, paragraph 104), a physical producer unit (router at source host, figure 5, paragraphs 52 - 53), and a physical consumer unit (router at destination host, figure 5, paragraphs 52 - 53) of the processor (host and port assigned to initial location 601 and connected to nearest routers with proposed relocation at 607, figure 6, flow mapped to 810 and routes updated properties, paragraphs 61, 70, 71, and 90); determine an upper bandwidth limit of the logical edge (ceiling bandwidth of NoC channel, paragraphs 17 and 18); determine all logical edges of the operation unit graph that are assigned to use the physical link (flow is mapped to route at 814 and flow updated where data structures tracking bandwidth of various channels so set of flows on a channel held, figure 8, paragraphs 16, 90, 92); determine a sum of realized average bandwidths of all the logical edges that are assigned to use the physical link to determine a congestion estimation of the physical link (bandwidth requirement at channel determined by flows over channel and bandwidth values over summation of bandwidths, figures 6 and 8, paragraphs 16, 62, and 67); and determine a realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge, the end-to-end bandwidth, the scaling factor of the realized bandwidth, and the congestion estimation of the physical link (paragraphs 16 and 17 congestion estimation levels with respect to capacity, figure 2b).
Kumar does not appear to explicitly disclose a reconfigurable processor, determine a scaling factor of a realized bandwidth; determine an end-to-end bandwidth between the physical producer unit and the physical consumer unit.
However, Schreiber discloses a reconfigurable processor (column 4, lines 15 – 18), determine a scaling factor of a realized bandwidth (estimated bandwidth traffic divided by estimated cycle count, iterations per tile times the initiation interval divided by number of processors, figures 3 and 5).
Kumar and Schreiber are analogous art because they are from the [insert the phrase same field of endeavor of processor handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kumar and Schreiber before him or her, to modify the flow handling of Kumar to include the bandwidth handling of Schreiber because it would enhance processing in a bandwidth dependent system.
One of ordinary skill would be motivated to make such modification in order to enhance processing of tasks (column 1, lines 26 – 63). Therefore, it would have been obvious to combine Schreiber with Kumar to obtain the invention as specified in the instant claims.
Kumar/Schreiber does not appear to explicitly disclose determine an end-to-end bandwidth between the physical producer unit and the physical consumer unit.
However, Barkey discloses determine an end-to-end bandwidth between the physical producer unit (sender 12, figure 1) and the physical consumer unit (receiver 14, figure 1, calculated segments for max depth in data segments of received data buffer 22, figure 1).
Kumar/Schreiber and Barkey are analogous art because they are from the same field of endeavor of data processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kumar/Schreiber and Barkey before him or her, to modify the bandwidth mechanism of Kumar/Schreiber to include the bandwidth management of Barkey because it would enhance overflow capabilities.
One of ordinary skill would be motivated to make such modification in order to enhance data integrity (column 2, lines 14 – 31). Therefore, it would have been obvious to combine Barkey with Kumar/Schreiber to obtain the invention as specified in the instant claims.
6. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 2, Schreiber teaches a method, wherein the reconfigurable processor (array 108 of data path elements 110, figure 1) comprises arrays of coarse-grained reconfigurable (CGR) units (processor elements each having local storage and one or more functional units, figures 1 and 11).
7. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 3, Kumar teaches a method, wherein the logical consumer unit comprises a compute unit (cpub1…4, figure 5a) or a memory unit (mema, memb, figure 5a).
8. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 4, Kumar teaches a method, further comprising: providing the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool (Soc 1011 and NoC 1012, figure 10, cost function is computed for the port at initial position vs proposed new position and relocation is accepted or rejected at 607 where each eligible route has cost function defined by routers, channels, latency and bandwidth, figure 6, 8, and 10, paragraphs 70, 71, 88, and 89).
9. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 5, Kumar teaches a method, wherein determining the end-to-end bandwidth between the physical producer unit and the physical consumer unit further comprises: in response to determining that the physical consumer unit is not end-to-end credit- controlled, determining the end-to-end bandwidth to be 1.0 (flow based bandwidth handling, paragraphs 18 and 19).
10. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 9, Schreiber teaches a method, wherein determining the scaling factor of the realized bandwidth further comprises: determining a number of active cycles of the logical edge (operation latency between sampling input and production result where edge of data flow graph carries and edge delay specifying min number of cycles, figure 4); determining a number of stage cycles (figures 3, 5, and 8); and determining the scaling factor of the realized bandwidth based on a division of the number of active cycles by the number of stage cycles (estimated bandwidth is estimated traffic with respect to cycle count where demand is scaled by a cycle ration based on initiation interval, figures 3 and 5).
11. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claims 11 and 19, Kumar teaches a method and system, wherein determining the upper bandwidth limit of the logical edge further comprises: determining an upper output bandwidth limit of the logical producer unit (ceiling bandwidth of NoC channel, paragraphs 17 and 18); determining an upper input bandwidth limit of the logical consumer unit (bandwidth upper input limit, paragraphs 18 and 19); and determining the upper bandwidth limit of the logical edge as a minimum of the upper output bandwidth limit and the upper input bandwidth limit (paragraphs 62 and 63).
12. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 12, Kumar teaches a method, wherein determining the congestion estimation of the physical link further comprises: determining a sum of realized average bandwidths of all the logical edges that are assigned to use the physical link (bandwidth requirement at channel determined by flow so load on all channels balanced, with associated assigned weight to host/port, figures 6 and 8, paragraphs 16, 62, and 67).
13. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 14, Kumar teaches a method, for determining the end-to-end bandwidth between the physical producer unit and the physical consumer unit, the cost estimation tool is further configured to: in response to determining that the physical consumer unit is end-to-end credit- controlled, determine the end-to-end bandwidth to be 100 percent (flow based bandwidth handling, paragraphs 18 and 19).
14. Kumar modified by the teachings of Schreiber/Barkey as seen in claim 1 above, as per claim 17, Schreiber teaches a system, wherein, for determining the scaling factor of the realized bandwidth, the cost estimation tool is further configured to: determine a number of active cycles of the logical edge (each dependence edge carries an edge delay specifying min number of cycles between initiation of predecessor and successor operations, paragraph 4); determine a number of stage cycles (count iteration per time and initiation interval over number of processors, figures 3 and 5); and determine the scaling factor of the realized bandwidth based on a division of the number of active cycles by the number of stage cycles (estimated bandwidth is estimated traffic over estimated cycle count, figure 3).
Allowable Subject Matter
15. Claims 6, 7, 8, 10, 15, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chofleming/Ebcioglu/Glendenning/Prabhakar/Rhoads/Sastry have producer consumer teachings with logical edge therein.
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/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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