DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (19/046,323) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
As a reminder, if the parent application issues before this application is allowed, paragraph 1 of the specification will be objected to for not including the patent number of the parent application.
The disclosure is objected to because of the following informalities:
In paragraph 3, “performs most of processing” is grammatically incorrect and must be reworded.
In paragraph 8, ln 3, insert --that-- before “points”.
In paragraph 13, “the instruction” lacks antecedent basis because multiple instructions are set forth in lines 1-2 of the paragraph.
In paragraph 18, insert --an-- after “depicts”.
In paragraph 19, insert --an-- after “depicts”.
In paragraph 20, insert --an-- after “depicts”.
In paragraph 51, replace “R2+R3=R1” with --R1=R2+R3--.
In paragraph 64, line 2, does applicant mean --in parallel-- instead of “in sequence”? If these two instructions are executed in sequence, it would appear there would be no conflict.
In paragraph 64, should “R6” and “R7” be --P6-- and --P7--, respectively?
In paragraph 69, please reword to --…destination, and R2 and R3 are sources…--.
In paragraph 69, replace “R2+R3=R1” with --R1=R2+R3--.
In paragraph 71, line 1, insert --be-- after “may”.
In paragraph 78, line 2, it appears that “separate” should be replaced with
--separated--.
In paragraph 78, last line, it appears that “architectural registers” can be deleted due to the same language used in the previous line.
In paragraph 93, 2nd to last sentence, replace “remap rename bank 0 to physical bank 5” with --rename bank 0 is remapped to physical bank 5--.
In paragraph 97, there is lack of antecedent basis for “the instruction” because multiple instructions are set forth in paragraph 95.
Paragraphs 111+ include similar language as the claims. Thus, they should be amended similar to the claims to address any objections/112 rejections set forth below. Please check other paragraphs as well for similar issues (e.g. paragraph 13).
Appropriate correction is required.
Drawings
FIG.5 is objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(L), which requires that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The examiner asserts that the quality of the mapping table (and numbers therein) is pixelated/noisy/fuzzy/blurry and slightly faded.
FIG.6 is objected to because of the following minor informalities:
In step 630, there is lack of antecedent basis for “the instruction” because multiple instructions are set forth in step 610.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Inquiries
Claims 7, 9, 12, 16, and 18 are objected to because of the following informalities:
In claim 7, line 4, replace “register” with --registers--.
In claim 7, line 5, replace “separate” with --separated--.
In claim 9, replace “writes results to” with --reads data from--.
In claim 12, it appears that a rename bank is a set of physical registers. Thus, replace “refers” with --is--, --comprises--, --includes-- (or the like).
In claim 16, replace “writes results to” with --reads data from--.
In claim 18, line 5, replace “separate” with --separated--.
Please confirm that claims 17-18 are indeed meant to depend on claim 1 as opposed to claim 11. If the dependency is correct, applicant is advised that, should claim 7 be found allowable, claims 17-18 will be objected to under 37 CFR 1.75 as being a substantial duplicate of claim 7. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 13, and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 1, last line, “the instruction”, because there is at least one instruction in line 2. Please insert --at least one-- before “instruction” in the last line.
In claim 8 (and similarly claim 15), “the multiple architectural register tags referenced by the destination operand”. Applicant never previously sets forth that the destination operand alone references multiple tags. Instead, applicant claims that at least one operand references multiple tags, and that a destination operand may be one of the operands. So, this would encompass having an instruction with a destination operand and a source operand, each referencing a single tag, such that the two operands reference multiple tags. The examiner will interpret the quoted phrase above as if “the” at the beginning were absent.
In claim 9 (and similarly claim 16), “the multiple architectural register tags referenced by the source operand” for similar reasoning. The examiner will interpret the quoted phrase above as if “the” at the beginning were absent.
In claim 13, “the physical registers from the set”. It isn’t clear whether applicant is referring to the physical regs from claim 11, which happen to be in the set, or if applicant is referring to all registers in the set.
In claim 19, last line, “the instruction”, because there are multiple instructions in line 2 and at least one instruction in line 5. It appears applicant should insert --at least one-- in the last line.
Claims 2-10, 17-18, and 20 are rejected due to their dependence on an indefinite claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 and 17-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 8-11, 8, 8, 12, and 14, respectively, of copending Application No. 19/046,323. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated by those of ‘323. Of note, renaming register tags is equivalent to renaming registers.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 11-16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 1, 6, and 9-10, respectively, of ‘323, in view of the examiner’s taking of Official Notice.
The differences between these claims include instant claim 11 requiring each register being mapped to a different rename bank and that dispatching occur to an MXU or LSU. With respect to the former, claim 1 of ‘323 includes a reference to two register tags, and if two register tags are renamed to physical tags in multiple rename banks, then each tag is mapped to a different rename bank. With respect to the latter, Official notice is taken that dispatching an instruction to such units was well known in the art before applicant’s invention. Such units allow for matrix math and loading/storing data from/to memory. Thus, to accommodate a particular type of math and to allow data transfer to/from external memory, it would have been obvious to one of ordinary skill in the art to modify claim 1 of ‘323 to dispatch to an MXU or LSU after mapping.
With respect to claim 12, a rename bank is a set of physical registers as is known in the art of renaming. Thus, this limitation in claim 12 is anticipated by claim 1 of ‘323.
With respect to claim 13, when mapping to physical register tags is mapping to a set of physical registers, as is known in the art of renaming. Thus, this limitation in claim 13 is anticipated by claim 1 of ‘323.
With respect to claim 14, when a banked freelist exists (as in claim 6 of ‘323), physical registers would be added to the freelist sometime after execution completes. Thus, this limitation in claim 14 is anticipated by claim 6 of ‘323.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gschwind et al. (2007/0260855), as cited by applicant.
Referring to claim 1, Gschwind has taught a method, comprising:
receiving at least one instruction that references multiple architectural registers (see paragraph [0060], which sets forth an instruction that references architectural registers r8, r9, r10, r11, r12, and r13 (since it is a combination of the instructions in paragraphs 58-59). At least some of these registers are the claimed “multiple architectural registers”. See paragraph 61 as well);
renaming the multiple architectural registers to physical registers organized in multiple rename banks (see FIG.6, map table 820, which renames registers (paragraph 120) that are split into even and odd register banks (paragraph 62)); and
dispatching the instruction for execution after the renaming (per paragraph 121, renamed instructions are stored into the dispatch table 824, from which they are dispatched for execution (e.g. by functional units 807)).
Referring to claim 2, Gschwind has taught the method of claim 1, further comprising using a mapping table to map architectural registers to physical registers for the renaming (see FIG.6, map table 820, and paragraphs 62 and 120).
Referring to claim 3, Gschwind has taught the method of claim 1, further comprising mapping each of the multiple architectural registers to a physical register in a different rename bank from the multiple rename banks for the renaming (again, in paragraph 60, when the multiple registers are r10 and r11, these are mapped to different physical banks so that they can be read at the same time while keeping ports to a minimum).
Referring to claim 4, Gschwind has taught the method of claim 1, further comprising mapping adjacent architectural registers from the multiple architectural registers to the physical registers in different rename banks from the multiple rename banks for the renaming (again, from paragraphs 58-62, adjacent registers r10 and r11 are mapped to even and odd banks. Similarly, r8 and r9 and also r12 and r13 would be mapped to the even and odd banks).
Referring to claim 5, Gschwind has taught the method of claim 3, wherein the mapping table has a fixed assignment from architectural registers to physical registers according to a (the mapping entries in the mapping table represent a fixed assignment of physical tags to architectural tags. And, the overall assignment is based on the total number of registers whose mappings are valid, i.e., those that have been mapped but not yet freed. In other words, if there are 12 architectural registers that have been renamed and none of the physical registers mapped thereto have been freed (since they are still in use), then 12 is a number on which the fixed assignment, i.e., 12 mappings, is based. Note further that struck-through claim language is alternative in nature and not required by the prior art).
Referring to claim 6, Gschwind has taught the method of claim 1, further comprising tracking unused physical registers using a banked freelist (FIG.6, free register queue 822).
Referring to claim 7, Gschwind has taught the method of claim 1, wherein:
the reference to the multiple architectural registers is subject to one or more restrictions (see paragraphs 62-63, which sets forth adjacent register tags (even and odd). This is the restriction which allows multiple instructions (in paragraphs 58-59) to be merged/paired into a single instruction (in paragraph 60)), and
the one or more restrictions restrict the multiple architectural registers to:
consecutive architectural register (again, see paragraphs 58-63. The r10 in paragraph 60 actually represents consecutive/adjacent registers r10 and r11 due to the restriction that allows the instructions of paragraphs 58-59 to be combined);
(this is an alternative limitation that is not required to be taught by the prior art).
Referring to claim 8, Gschwind has taught the method of claim 1, wherein:
the at least one instruction has at least one operand that references the multiple architectural registers (see paragraph 60, destination operand r8, which actually represents destinations r8 and r9);
the at least one operand comprises a destination operand (again, see paragraph 60, destination operand r8, which actually represents destinations r8 and r9); and
the at least one instruction involves a vector operation that writes results to the multiple architectural registers referenced by the destination operand (a vector of two 64-bit elements is written to the r8 and r9 destinations).
Referring to claim 9, Gschwind has taught the method of claim 1, wherein:
the at least one instruction has at least one operand that references the multiple architectural registers (see paragraph 60, source operand r10, which actually represents sources r10 and r11);
the at least one operand comprises a source operand (again, see paragraph 60, source operand r10, which actually represents sources r10 and r11); and
the at least one instruction involves a vector operation that reads data from the multiple architectural registers referenced by the source operand (a vector of input data is read from sources r10 and r11 and added to other data (from registers r12 and r13)).
Referring to claim 10, Gschwind has taught the method of claim 1, further comprising obtaining a sequence of instructions that includes an instruction that has operands that each only reference a single architectural register (see paragraph 58 for an example. Operands r8, r10, and r12, each only reference a single tag. The sequence of instructions in paragraphs 58-59 is obtained and combined to form the instruction in paragraph 60).
Referring to claim 11, Gschwind has taught a method, comprising:
obtaining a sequence of instructions that includes at least one instruction that has at least one operand that references multiple architectural registers (see the PLFU instruction in paragraph 81-84, where the PLFU has an operand FR that actually references registers FR and FR+1);
mapping the multiple architectural registers to physical registers organized in multiple rename banks, wherein each of the multiple architectural registers is mapped to a physical register in a different rename bank from the multiple rename banks (see FIG.6, map table 820, which renames registers (paragraph 120) that are split into even and odd register banks (paragraph 62) so that they can be written at the same time while keeping ports to a minimum); and
dispatching the at least one instruction for execution to at least one of a matrix processing unit (MXU) or a load store unit (LSU) after the mapping (the PLFU is a load instruction and would therefore be dispatched to a LSU for execution).
Referring to claim 12, Gschwind has taught the method of claim 11, wherein at least one rename bank of the multiple rename banks refers to a set of physical registers configured to store values for one or more instructions (the odd and even banks are physical banks of registers where operands and results are stored for instructions).
Referring to claim 13, Gschwind has taught the method of claim 11, further comprising:
determining a set of available physical registers from the multiple rename banks (as the instruction of paragraph 83 will write to FR and FR+1, a set of two physical registers, one from the odd bank and one from the even bank, will be determined); and
allocating the physical registers from the set of available physical registers for the mapping (the set of two physical registers will be allocated to the instruction to load the pair of values).
Referring to claim 14, Gschwind has taught the method of claim 11, further comprising at least one of: tracking the mapping of the multiple architectural registers to the physical registers (paragraph 120);(note the struck-through alternative is not required to be taught by the prior art).
Referring to claim 15, Gschwind has taught the method of claim 11, wherein:
the at least one operand comprises a destination operand (in paragraph 83, FR is a destination register operand); and
the at least one instruction involves a vector operation that writes results to the multiple architectural registers referenced by the destination operand (in paragraphs 81-84, the FR operand of the PLFU instruction references FR and FR+1, to which a vector of loaded elements are loaded).
Referring to claim 16, Gschwind has taught the method of claim 11, wherein:
the at least one operand comprises a source operand (from paragraph 88, the instruction may include a store instruction and be implemented as the load instruction of example 6 in paragraph 83. One of ordinary skill in the art would recognize that such an implementation is the opposite of a load and would thus specify a source register that indicates multiple source registers from which data is read to be stored to memory); and
the at least one instruction involves a vector operation that writes results to the multiple architectural registers referenced by the source operand (similar to paragraph 83, a store instruction would store a vector of elements from FR and FR+1 into memory addresses).
Claim 17 is rejected for similar reasoning as claim 7.
Claim 18 is rejected for similar reasoning as claim 7, where the stride is set such that the registers are consecutive.
Claim 19 is mostly rejected for similar reasoning as claim 1. Gschwind has further taught:
a memory comprising instructions (FIG.6, memory 801, from which instructions are fetched (paragraph 119). There is also at least cache memory (paragraph 37, FIG.5, 704), instruction queue (FIG.5, 703)); and
one or more processors (FIG.6, processor 800), individually or collectively, configured to execute the instructions and cause the apparatus to perform the claimed operations (a processor executes instructions to obtain instructions and carry out renaming and dispatching thereof).
Claim 20 is mostly rejected for similar reasoning as claim 3. Again, executed code from memory configures the processor(s) to perform operations.
Conclusion
The prior art made of record by applicant includes prior art cited by the examiner in the parent application. Given the similarity of the claims between the two applications, the art cited by the examiner in the parent is pertinent for reasons set forth in paragraph 37 of the Office Action mailed on May 5, 2026, in the parent application. Applicant’s attention is directed to that reasoning.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
