DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to the Preliminary Amendment dated 6/9/2025.
Claims 1-20 are cancelled.
Claims 21-40 are added.
Claims 21-40 are pending.
Claims 21, 32, and 36 are rejected.
Information Disclosure Statement
The information disclosure statements (IDSes) submitted on 7/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21, 32, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over non-patent literature "In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures" ("Masing") in view of non-patent literature "A Hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications" ("Lusala") and further in view of non-patent literature "VERSAL NETWORK-on-CHIP (NoC)" ("Swarbrick").
As per claim 21, Masing substantially teaches an integrated circuit device (Masing, page 2, Fig. 1), comprising:
a processing element; a plurality of memory controllers; and a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network, wherein the second network includes a crossbar: (Masing, page 1, column 1, section "Abstract;" page 2, Fig. 1; page 2, column 1, section "III. THE NoC ARCHITECTURE," paragraphs 1-2; and page 2, column 2, section "A. The in-NoC-Circuits," paragraphs 1-2; and page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1, where the system of Masing uses tiles that each comprise processing elements, private L1 caches, intra-tile L1 caches, a shared L2 cache, and a tile local memory (TLM). The Examiner notes that each tile comprises a TLM, which means that each tile must comprise a memory controller for controlling the TLM associated with the each tile. The Examiner further notes that the system of Masing is a tile-based uses a network-on-chip (NoC) to enable communication among tiles. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The Examiner further notes that each element of the PS layer must comprise at least one routing table in order to correctly route packets of the PS layer to a correct destination. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. Masing therefore substantially teaches a processing element; a plurality of memory controllers; and a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network, wherein the second network includes a crossbar).
Masing does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Lusala teaches a hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications.
As per claim 21, Lusala particularly teaches:
and wherein the crossbar connects the processing element to any memory controller of the plurality of memory controllers while maintaining a same delay for the path: (Lusala, page 1, column 1, section "Abstract;" page 1, columns 1-2, section "I. INTRODUCTION," paragraphs 1-5; page 2 columns 1-2, section "A. Router architecture," paragraphs 1-3; page 2, column 2, section "B. Packet-Switched sub-router," paragraphs 1-5; and page 3, column 2, to page 4, column 1, section "C. SDM-Based Circuit-Switched sub-router," paragraphs 1-4, where the NoC of Lusala comprises both a packet-switched segment and a circuit-switched segment for respectively handling connectionless best-effort traffic and connection-based streaming traffic. From the perspective of a given tile, performance is the same whether the packet-switched segment is used or the circuit-switched segment is used. Lusala therefore particularly teaches and wherein the crossbar connects the processing element to any memory controller of the plurality of memory controllers while maintaining a same delay for the path).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lusala and Masing before them before the instant application was effectively filed, to modify the system of Masing to include the principles of Lusala of utilizing both packet-switched and circuit-switched networks to efficiently handle traffic within a NoC.
The modification would have been obvious because a person having ordinary skill in the art would have been motivated to increase system flexibility and performance by implementing a hybrid network-on-chip (NoC) that combines circuit-switching and packet-switching to efficiency and separately handle streaming and best-effort traffics generated by real-time applications (Lusala, page 1, column 1, section "Abstract").
Neither Masing nor Lusala appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Swarbrick teaches Versal Network-on-Chip (NOC).
As per claim 21, Swarbrick particularly teaches:
wherein the NoC is configured to implement a path coupling the processing element and the plurality of memory controllers in which a first portion of the part is implemented in the first network and a second portion of the path is implemented in the second network: (Swarbrick, page 1, section "Abstract"; pages 2, sections "1.3 NoC Overview and Features" and "1.4 Routing and Topology," where the Bersal NoC of Swarbrick may include crossbar switches (i.e., non-blocking elements) and packet routing elements (i.e., sparse network elements) that enable components within the Versal system (e.g., memory controllers and memory chips) to communicate over multiple paths. Swarbrick therefore particularly teaches wherein the NoC is configured to implement a path coupling the processing element and the plurality of memory controllers in which a first portion of the part is implemented in the first network and a second portion of the path is implemented in the second network).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Swarbrick, Lusala, and Masing before them before the instant application was effectively filed, to modify the combination of Lusala with Masing to include the principles of Swarbrick of a Versal NoC that enables communication between memory controllers and memory.
The modification would have been obvious because a person having ordinary skill in the art would have been motivated to increase system flexibility and performance by implementing programmable accelerator logic that may be customized to accelerate a whole application (Swarbrick, page 1, section "Abstract").
As per claim 32, Masing substantially teaches an integrated circuit device (Masing, page 2, Fig. 1), comprising;
a plurality of processing elements; a plurality of memory controllers; and a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network, wherein the second network includes a plurality of crossbars, wherein each crossbar of the plurality of crossbars is coupled to a subset of the plurality of memory controllers: (Masing, page 1, column 1, section "Abstract;" page 2, Fig. 1; page 2, column 1, section "III. THE NoC ARCHITECTURE," paragraphs 1-2; and page 2, column 2, section "A. The in-NoC-Circuits," paragraphs 1-2; and page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1, where the system of Masing uses tiles that each comprise processing elements, private L1 caches, intra-tile L1 caches, a shared L2 cache, and a tile local memory (TLM). The Examiner notes that each tile comprises a TLM, which means that each tile must comprise a memory controller for controlling the TLM associated with the each tile. The Examiner further notes that the system of Masing is a tile-based uses a network-on-chip (NoC) to enable communication among tiles. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The Examiner further notes that each element of the PS layer must comprise at least one routing table in order to correctly route packets of the PS layer to a correct destination. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. Masing therefore substantially teaches a plurality of processing elements; a plurality of memory controllers; and a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network, wherein the second network includes a plurality of crossbars, wherein each crossbar of the plurality of crossbars is coupled to a subset of the plurality of memory controllers).
Masing does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Lusala teaches a hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications.
As per claim 32, Lusala particularly teaches:
and wherein each crossbar is programmable to connect a first portion of a path to any one of the subset of the plurality of memory controllers coupled to the crossbar: (Lusala, page 1, column 1, section "Abstract;" page 1, columns 1-2, section "I. INTRODUCTION," paragraphs 1-5; page 2 columns 1-2, section "A. Router architecture," paragraphs 1-3; page 2, column 2, section "B. Packet-Switched sub-router," paragraphs 1-5; and page 3, column 2, to page 4, column 1, section "C. SDM-Based Circuit-Switched sub-router," paragraphs 1-4, where the NoC of Lusala comprises both a packet-switched segment and a circuit-switched segment for respectively handling connectionless best-effort traffic and connection-based streaming traffic. From the perspective of a given tile, performance is the same whether the packet-switched segment is used or the circuit-switched segment is used. Lusala therefore particularly teaches and wherein each crossbar is programmable to connect a first portion of a path to any one of the subset of the plurality of memory controllers coupled to the crossbar).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lusala and Masing before them before the instant application was effectively filed, to modify the system of Masing to include the principles of Lusala of utilizing both packet-switched and circuit-switched networks to efficiently handle traffic within a NoC.
The modification would have been obvious because a person having ordinary skill in the art would have been motivated to increase system flexibility and performance by implementing a hybrid network-on-chip (NoC) that combines circuit-switching and packet-switching to efficiency and separately handle streaming and best-effort traffics generated by real-time applications (Lusala, page 1, column 1, section "Abstract").
Neither Masing nor Lusala appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Swarbrick teaches Versal Network-on-Chip (NOC).
As per claim 32, Swarbrick particularly teaches:
wherein the plurality of processing elements are coupled to the plurality of memory controllers via a plurality of paths each having a first portion implemented in the first network and a second portion implemented using a selected crossbar of the plurality of crossbars of the second network: (Swarbrick, page 1, section "Abstract"; pages 2, sections "1.3 NoC Overview and Features" and "1.4 Routing and Topology," where the Bersal NoC of Swarbrick may include crossbar switches (i.e., non-blocking elements) and packet routing elements (i.e., sparse network elements) that enable components within the Versal system (e.g., memory controllers and memory chips) to communicate over multiple paths. Swarbrick therefore particularly teaches wherein the plurality of processing elements are coupled to the plurality of memory controllers via a plurality of paths each having a first portion implemented in the first network and a second portion implemented using a selected crossbar of the plurality of crossbars of the second network).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Swarbrick, Lusala, and Masing before them before the instant application was effectively filed, to modify the combination of Lusala with Masing to include the principles of Swarbrick of a Versal NoC that enables communication between memory controllers and memory.
The modification would have been obvious because a person having ordinary skill in the art would have been motivated to increase system flexibility and performance by implementing programmable accelerator logic that may be customized to accelerate a whole application (Swarbrick, page 1, section "Abstract").
As per claim 36, Masing substantially teaches a method (Masing, page 1, column 1, section "Abstract"), comprising:
submitting a memory access request from a processing element; routing the memory access request over a path through a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables that implement a first portion of the path and a second network coupled to the first network, wherein the second network includes a crossbar and implements a second portion of the path: (Masing, page 1, column 1, section "Abstract;" page 2, Fig. 1; page 2, column 1, section "III. THE NoC ARCHITECTURE," paragraphs 1-2; page 2, column 2, section "A. The in-NoC-Circuits," paragraphs 1-2; and page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1, where the system of Masing uses tiles that each comprise processing elements, private L1 caches, intra-tile L1 caches, a shared L2 cache, and a tile local memory (TLM). The Examiner notes that each tile comprises a TLM, which means that each tile must comprise a memory controller for controlling the TLM associated with the each tile for enabling access by applications to the TLM. The Examiner further notes that the system of Masing is a tile-based uses a network-on-chip (NoC) to enable communication among tiles. In addition, (page 2, Fig. 1; and page 2, column 2, section "A. The in-NoC-circuits," paragraphs 1-2) teaches where applications executing on tiles have a means of communicating via the PS layer of the NoC of Masing. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The Examiner further notes that each element of the PS layer must comprise at least one routing table in order to correctly route packets of the PS layer to a correct destination. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. In addition, (Masing, page 3, Fig. 2; and page 3, column 1, section "B. Basic router architecture," to page 3, column 2, section "C. CS/PS link," paragraph 1) teaches where the system of Masing comprises a NoC that comprises a Packet-Switched (PS) layer and a Circuit-Switched (CS) layer. The PS layer is connected to the processing elements of tiles in order to allow the processing elements of the tiles to communicate with each other. The Examiner notes that the PS layer is a sparse network that connects the processing elements of the tile. The CS layer utilizes a crossbar to connect the sparse network of processing elements of a tile to the TLM of the tile. The Examiner notes that crossbars by definition are non-blocking. Masing therefore substantially teaches submitting a memory access request from a processing element; routing the memory access request over a path through a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables that implement a first portion of the path and a second network coupled to the first network, wherein the second network includes a crossbar and implements a second portion of the path).
Masing does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Lusala teaches a hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications.
As per claim 36, Lusala particularly teaches
wherein the crossbar is programmable to convey the memory access request to any memory controller of the plurality of memory controllers while maintaining a same delay for the path: (Lusala, page 1, column 1, section "Abstract;" page 1, columns 1-2, section "I. INTRODUCTION," paragraphs 1-5; page 2 columns 1-2, section "A. Router architecture," paragraphs 1-3; page 2, column 2, section "B. Packet-Switched sub-router," paragraphs 1-5; and page 3, column 2, to page 4, column 1, section "C. SDM-Based Circuit-Switched sub-router," paragraphs 1-4, where the NoC of Lusala comprises both a packet-switched segment and a circuit-switched segment for respectively handling connectionless best-effort traffic and connection-based streaming traffic. From the perspective of a given tile, performance is the same whether the packet-switched segment is used or the circuit-switched segment is used. Lusala therefore particularly teaches wherein the crossbar is programmable to convey the memory access request to any memory controller of the plurality of memory controllers while maintaining a same delay for the path).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lusala and Masing before them before the instant application was effectively filed, to modify the system of Masing to include the principles of Lusala of utilizing both packet-switched and circuit-switched networks to efficiently handle traffic within a NoC.
The modification would have been obvious because a person having ordinary skill in the art would have been motivated to increase system flexibility and performance by implementing a hybrid network-on-chip (NoC) that combines circuit-switching and packet-switching to efficiency and separately handle streaming and best-effort traffics generated by real-time applications (Lusala, page 1, column 1, section "Abstract").
Neither Masing nor Lusala appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Swarbrick teaches Versal Network-on-Chip (NOC).
As per claim 36, Swarbrick particularly teaches:
conveying, by the crossbar, the memory access request to a selected memory controller of a plurality of memory controllers coupled to the crossbar: (Swarbrick, page 1, section "Abstract"; pages 2, sections "1.3 NoC Overview and Features" and "1.4 Routing and Topology," where the Bersal NoC of Swarbrick may include crossbar switches (i.e., non-blocking elements) and packet routing elements (i.e., sparse network elements) that enable components within the Versal system (e.g., memory controllers and memory chips) to communicate over multiple paths. Swarbrick therefore particularly teaches conveying, by the crossbar, the memory access request to a selected memory controller of a plurality of memory controllers coupled to the crossbar).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Swarbrick, Lusala, and Masing before them before the instant application was effectively filed, to modify the combination of Lusala with Masing to include the principles of Swarbrick of a Versal NoC that enables communication between memory controllers and memory.
The modification would have been obvious because a person having ordinary skill in the art would have been motivated to increase system flexibility and performance by implementing programmable accelerator logic that may be customized to accelerate a whole application (Swarbrick, page 1, section "Abstract").
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21, 32, and 36 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 14 of U.S. Patent No. 12,353,717 (“Gupta”). The following tables, in which similarities between claims 21, 32, and 36 of the instant application and claims
of 1 and 14 of Gupta are highlighted in bold, and accompany reasoning show that claims 21, 32, and 36 of the instant application are not patentably distinct from claims 1 and 14 of Gupta:
Instant Application, Claim 21
Gupta, Claim 1
21. An integrated circuit device, comprising: a processing element; a plurality of memory controllers; and a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network, wherein the second network includes a crossbar; wherein the NoC is configured to implement a path coupling the processing element and the plurality of memory controllers in which a first portion of the path is implemented in the first network and a second portion of the path is implemented in the second network; and wherein the crossbar connects the processing element to any memory controller of the plurality of memory controllers while maintaining a same delay for the path.
1. A system, comprising: a plurality of processing elements; a plurality of memory controllers; and a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers, the NoC including: a sparse network coupled to the plurality of processing elements, wherein the sparse network includes a plurality of interconnected switches having routing tables; and a non-blocking network coupled to the sparse network and the plurality of memory controllers, wherein the non-blocking network includes a plurality of crossbars, each crossbar couples the sparse network to a subset of the plurality of memory controllers, and each subset includes at least a first memory controller and a second memory controller; wherein the sparse network implements a first portion of a path coupling one or more selected processing elements of the plurality of processing elements to the non-blocking network, the non-blocking network implements a second portion of the path, and a crossbar of the second portion of the path connects the one or more selected processing elements to the first memory controller or the second memory controller while maintaining a same delay for memory access performance.
Claim 1 of Gupta does not appear to explicitly claim an integrated circuit device; however, claim 1 of Gupta explicitly claims a system that comprises a plethora of integrated circuit devices. It would have been obvious to a person having ordinary skill in the art before the instant application was effectively filed to implement the system of claim 1 of Gupta as an integrated circuit device because a person having ordinary skill in the art before the instant application was effectively filed would be motivated to increase system flexibility by using an integrated circuit device as one design choice for implementing the system of claim 1 of Gupta.
Instant Application, Claim 32
Gupta, Claim 1
32. An integrated circuit device, comprising: a plurality of processing elements; a plurality of memory controllers; and a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network, wherein the second network includes a plurality of crossbars; wherein each crossbar of the plurality of crossbars is coupled to a subset of the plurality of memory controllers; wherein the plurality of processing elements are coupled to the plurality of memory controllers via a plurality of paths each having a first portion implemented in the first network and a second portion implemented using a selected crossbar of the plurality of crossbars of the second network; and wherein each crossbar is programmable to connect a first portion of a path to any one of the subset of the plurality of memory controllers coupled to the crossbar.
1. A system, comprising: a plurality of processing elements; a plurality of memory controllers; and a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers, the NoC including: a sparse network coupled to the plurality of processing elements, wherein the sparse network includes a plurality of interconnected switches having routing tables; and a non-blocking network coupled to the sparse network and the plurality of memory controllers, wherein the non-blocking network includes a plurality of crossbars, each crossbar couples the sparse network to a subset of the plurality of memory controllers, and each subset includes at least a first memory controller and a second memory controller; wherein the sparse network implements a first portion of a path coupling one or more selected processing elements of the plurality of processing elements to the non-blocking network, the non-blocking network implements a second portion of the path, and a crossbar of the second portion of the path connects the one or more selected processing elements to the first memory controller or the second memory controller while maintaining a same delay for memory access performance.
Claim 1 of Gupta does not appear to explicitly claim an integrated circuit device; however, claim 1 of Gupta explicitly claims a system that comprises a plethora of integrated circuit devices. It would have been obvious to a person having ordinary skill in the art before the instant application was effectively filed to implement the system of claim 1 of Gupta as an integrated circuit device because a person having ordinary skill in the art before the instant application was effectively filed would be motivated to increase system flexibility by using an integrated circuit device as one design choice for implementing the system of claim 1 of Gupta.
Instant Application, Claim 36
Gupta, Claim 14
36. A method, comprising: submitting a memory access request from a processing element; routing the memory access request over a path through a network on chip (NoC) having a first network including a plurality of interconnected switches having routing tables that implement a first portion of the path and a second network coupled to the first network, wherein the second network includes a crossbar and implements a second portion of the path; and conveying, by the crossbar, the memory access request to a selected memory controller of a plurality of memory controllers coupled to the crossbar, wherein the crossbar is programmable to convey the memory access request to any memory controller of the plurality of memory controllers while maintaining a same delay for the path.
14. A method, comprising: executing, by a plurality of processing elements, a plurality of applications; submitting, from the plurality of applications, memory access requests to a plurality of memory controllers; and routing the memory access requests through a network-on-chip (NoC) to the plurality of memory controllers, wherein the NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers; wherein the sparse network includes a plurality of interconnected switches having routing tables and wherein the non-blocking network includes a plurality of crossbars, each crossbar couples the sparse network to a subset of the plurality of memory controllers, and each subset includes at least a first memory controller and a second memory controller; wherein the routing conveys at least one of the memory access requests from one or more selected processing elements of the plurality of processing elements through a first portion of a path implemented by the sparse network and a second portion of the path implemented by the non-blocking network to a first memory controller of the subset coupled to the crossbar of the path; and configuring the crossbar of the path to connect the second memory controller of the subset while maintaining a same delay for memory access performance as for the first memory controller.
Claim 14 of Gupta does not appear to explicitly claim an integrated circuit device; however, claim 14 of Gupta explicitly claims a system that comprises a plethora of integrated circuit devices. It would have been obvious to a person having ordinary skill in the art before the instant application was effectively filed to implement the system of claim 14 of Gupta as a method for an integrated circuit device because a person having ordinary skill in the art before the instant application was effectively filed would be motivated to increase system flexibility by using an integrated circuit device as one design choice for implementing the method of claim 14 of Gupta.
Allowable Subject Matter
Claims 22-31, 33-35, and 37-40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and all intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
Prosecution Insights