DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 10-14, and 21-35 as amended in applicant’s response filed 14 September 2026 are presently under consideration. Claims 1-9 and 15-20 remain cancelled.
Applicant’s amendments to the claims have overcome the prior art grounds of rejection of record.
Upon performing updated search and consideration of applicant’s newly amended claims, new prior art was uncovered and a new grounds of rejection is set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lofgreen et al (US 2020/0312742), in further view of Huang et al (US 2021/0013191), and further in view of Scullin (US 2011/0114146) as further evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation).
Regarding claim 10 Lofgreen discloses a method of forming a package structure, comprising:
bonding a first package component to a circuit substrate through a plurality of first conductive connectors ([0053], Fig. 2 see: IC die 202 bonded to substrate 203 through interconnect layer 207);
forming a first thermoelectric cooler aside the plurality of first conductive connectors ([0053], Fig. 2 see: TECs 206), wherein the first thermoelectric cooler is vertically sandwiched between the first package component and the circuit substrate ([0053], Fig. 2 see: TECs 206 formed aside the interconnects of layer 207 between IC die 202 and substrate 203); and
forming a first underfill layer to laterally encapsulate the plurality of first conductive connectors and the first thermoelectric cooler, and continuously extending between the plurality of first conductive connectors and the first thermoelectric cooler ([0043]-[0044] see: an underfill material can further be present at the interface the TEC is disposed and thus considered to continuously extending between the interconnects and the TEC) but Lofgreen does not explicitly disclose said first underfill layer further extends to cover a lower sidewall of the first package component.
Huang discloses a method of forming a package structure, comprising forming a first underfill layer to continuously extend between a plurality of first conductive connectors and first device and further extend to cover a lower sidewall of a first package component (Huang, [0042]-[0043] Fig. 1H see: underfill layer 206 continuously extending between conductive connectors 204 and passive device 120 and further extending to cover a lower sidewall of upper package 10c).
Huang and Lofgreen are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Lofgreen in view of Huang such that the first underfill layer further extends to cover a lower sidewall of the first package component of Lofgreen as in Huang (Huang, [0042]-[0043] Fig. 1H see: underfill layer 206 continuously extending between conductive connectors 204 and passive device 120 and further extending to cover a lower sidewall of upper package 10c) as such a modification would have amounted to use of a known underfill layer structure in the known environment of a package structure for its intended use to accomplish the entirely expected result of providing mechanical reinforcement to the interconnect layer.
Modified Lofgreen does not explicitly disclose forming the first thermoelectric cooler comprises: performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate.
However, Scullin discloses a method for forming a first thermoelectric cooler (para [0026]) comprising performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate (Scullin, [0027]-[0029], Figs. 1, 3D, 4 see: providing substrate material (101), forming first regions with n-type semiconductor characteristics (113), forming second regions with p-type semiconductor characteristics (114), separated by intermediate regions 117 of the substrate material re-configured or functionalized to be a substantial electric insulator and a good thermal isolator) which is further evidenced by Strasser to be formed in silicon substrates (Strasser, see page 3 of translation, Figs. 2-4, see: thermoelectric device formed by doping body silicon layer of silicon blocks 10 with a first doping process 8 forming n-doped sections 12 and second doping process 9 forming p-doped sections 11 both separated by undoped sections 13).
Scullin discloses this method of manufacture for thermoelectric coolers reduces the process complexity, number of steps, and cost of production (paras [0021]-[0022]).
Scullin, Strasser and modified Lofgreen are combinable as they are all concerned with the field of thermoelectric device manufacture.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Lofgreen in view of Scullin as evidenced by Strasser such that the method of manufacturing the first thermoelectric cooler of Lofgreen comprises performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate as taught by Scullin ([0027]-[0029], Figs. 1, 3D, 4 see: providing substrate material (101), forming first regions with n-type semiconductor characteristics (113), forming second regions with p-type semiconductor characteristics (114), separated by intermediate regions 117 of the substrate material re-configured or functionalized to be a substantial electric insulator and a good thermal isolator) and as further evidenced by Strasser to be formed in silicon substrates (Strasser, see page 3 of translation, Figs. 2-4, see: thermoelectric device formed by doping body silicon layer of silicon blocks 10 with a first doping process 8 forming n-doped sections 12 and second doping process 9 forming p-doped sections 11 both separated by undoped sections 13) as Scullin discloses this method of manufacture for thermoelectric coolers reduces the process complexity, number of steps, and cost of production (paras [0021]-[0022]).
Regarding claim 11 modified Lofgreen discloses the method of claim 10, wherein the plurality of N-type doped regions and the plurality of P-type doped regions are connected to each other in series (Scullin, [0029]-[0030], Fig. 1 see: n-type regions 113 and p-type regions 115 connected in series by conductor shunts 123 and 125), the first thermoelectric cooler is configured to form a temperature gradient across a top surface and the bottom surface of the first thermoelectric cooler when a voltage is applied across the plurality of N-type doped regions and the plurality of P- type doped regions (Lofgreen, [0060] Fig. 2, see: TECs 206 when powered by TEC controller 220 form a temperature gradient to cool the front side 210 of IC die 202 and pump heat to via stacks 217).
Claims 12-14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lofgreen et al (US 2020/0312742) in view of Huang et al (US 2021/0013191) in view of Scullin (US 2011/0114146) as evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation) as applied to claims 10-11 above, and further in view of Yu’807 (US 2017/0345807) and in further view of Mittal et al (US 2016/0334845).
Regarding claim 12 modified Lofgreen discloses the method of claim 10, wherein the first package component comprises:
a die (Lofgreen, [0053], Fig. 2 see: IC die 202); and
Huang discloses first package component comprising an encapsulant, laterally encapsulating the die (Huang, [0040], Fig. 1H see: encapsulant 208 laterally encapsulating dies 200a, 200b or encapsulant 108 laterally encapsulating die 100).
Modified Lofgreen does not explicitly disclose where the die is vertically disposed between a first RDL structure and a second RDL structure and wherein the first thermoelectric cooler is bonded onto the first RDL structure by a first adhesive structure, and bonded onto the circuit substrate by a second adhesive structure.
Yu’807 discloses a package structure comprising a die vertically disposed between a first RDL structure and a second RDL structure (Yu’807, [0023], [0034], [0039] Figs. 12-14 see: device dies 234 of secondary package 200 comprising first RDLs 52 and second RDLs 92 or see in Fig. 11A see: Redistribution Lines (RDLs) 52 and 70 on device dies 58 and encapsulating material 66). Yu’807 teaches this stacking structure allows for a very thin package (Yu’807, [0037]).
Yu’807 and modified Lofgreen are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Lofgreen in view of Yu’807 such that the die of Lofgreen is vertically disposed between a first RDL structure and a second RDL structure as in Yu’807 (Yu’807, [0023], [0034], [0039] Figs. 12-14 see: device dies 234 of secondary package 200 comprising first RDLs 52 and second RDLs 92 or see in Fig. 11A see: Redistribution Lines (RDLs) 52 and 70 on device dies 58 and encapsulating material 66) for the purpose of providing interconnections to upper or lower package structures or devices or as such a structure allows for very thin package stacking as taught by Yu’807 ([0037]).
Furthermore, Mittal teaches in package structures with thermoelectric coolers, the thermoelectric coolers can be adhered at its upper and lower surfaces through a first adhesive structure and a second adhesive structure (Mittal, [0038], [0046], Fig. 2 see: TEC 210 bonded at upper and lower surfaces through adhesive 270 and adhesive 272).
Mittal and modified Lofgreen are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Lofgreen in view of Mittal such that the first thermoelectric cooler of modified Lofgreen is bonded onto the first RDL structure of modified Lofgreen by a first adhesive structure, and bonded onto the circuit substrate of modified Lofgreen by a second adhesive structure as taught by Mittal ([0038], [0046], Fig. 2 see: TEC 210 bonded at upper and lower surfaces through adhesive 270 and adhesive 272) as such a modification would have amounted to the use of a known thermal interface bonding material for its intended use in a known environment of a semiconductor package structure to accomplish the entirely expected result of adhering the thermoelectric cooler to device interfaces for cooling while providing a thermally conductive interface for heat transfer.
Regarding claim 13 modified Lofgreen discloses the method of claim 12, and Yu’807 discloses further comprising:
bonding a second package component to the second RDL structure through a plurality of second conductive connectors (Yu’807, [0034], Figs. 10-11A see: bonding package 200 to RDLs 52 through solder regions 84); and
forming a second underfill layer to laterally encapsulate the plurality of second conductive connectors, and continuously extend between the plurality of second conductive connectors (Yu’807, [0034], Fig. 11A see: forming underfill 86 laterally encapsulating and continuously extending between solder regions 84),
Yu’807 or modified Lofgreen does not explicitly disclose wherein the second underfill layer further extends to cover a lower sidewall of the second package component, but as Huang already teaches where such underfill layers can further extends to cover a lower sidewall of a package component (Huang, [0042]-[0043] Fig. 1H see: underfill layer 206 continuously extending between conductive connectors 204 and further extending to cover a lower sidewall of upper package 10c), it would have been obvious to one having ordinary skill in the art at the time of the invention to further modify the method of Lofgreen in view of Huang such that the second underfill layer further extends to cover a lower sidewall of the second package component as in Huang above, as such a modification would have amounted to use of a known underfill layer structure in the known environment of a package structure for its intended use to accomplish the entirely expected result of providing mechanical reinforcement to the interconnect layer.
Regarding claim 14 modified Lofgreen discloses the method of claim 13, and regarding the claim 14 recitation “further comprising” forming a second thermoelectric cooler laterally between the plurality of second conductive connectors, wherein the second thermoelectric cooler is directly over the die“ Mittal teaches package structures can include multiple thermoelectric coolers (Fig. 21 see: TECs 2150, 2110, 2112) including a thermoelectric cooler laterally between the plurality of second conductive connectors between stacked package structures directly over the die of the lower package (Mittal, [0140]-[0147], Fig. 21, see: either of TECs 2110 or 2112 provided directly over first die 2122 or second die 2123 between conductive connections mounting first package 2102 to second package 2104). Mittal teaches these thermoelectric coolers can be bidirectional to dynamically dissipate heat back and forth between the stacked packages (paras [0143]-[0147]).
As such, it would have been obvious to one having ordinary skill in the art at the time of the invention to further modify the method of Lofgreen in view of Mittal to further comprise forming a second thermoelectric cooler laterally between the plurality of second conductive connectors, wherein the second thermoelectric cooler is directly over the die as in Mittal (Mittal, [0140]-[0147], Fig. 21, see: either of TECs 2110 or 2112 provided directly over first die 2122 or second die 2123 between conductive connections mounting first package 2102 to second package 2104) as Mittal teaches these thermoelectric coolers can be bidirectional to dynamically dissipate heat back and forth between the stacked packages (paras [0143]-[0147]).
Regarding claim 21 modified Lofgreen discloses the method of claim 12, wherein a vertical projection of the first thermoelectric cooler and a vertical projection of the die are overlapped to each other (Lofgreen, [0053], Fig. 2 see: TECs 206 overlap IC die 202 in the Z axis).
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lofgreen et al (US 2020/0312742) in view of Huang et al (US 2021/0013191) in view of Scullin (US 2011/0114146) as evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation) in view of Yu’807 (US 2017/0345807) in view of Mittal et al (US 2016/0334845) as applied to claims 10-14 and 21 above, and further in view of Lee et al (KR 20150007827A, reference made to attached English machine translation).
Regarding claims 22 and 23 modified Lofgreen discloses the method of claim 12, wherein the first adhesive structure comprises a first thermal interface material (TIM) (Mittal, [0038], [0046], Fig. 2 see: adhesive 270 and adhesive 272 each are a thermally conductive adhesive (thermal interface material)) but does not explicitly disclose where said first TIM is sandwiched between two first metal layers, and the two first metal layers are electrically floating. Modified Lofgreen discloses wherein the second adhesive structure comprises a second TIM (Mittal, [0038], [0046], Fig. 2 see: adhesive 270 and adhesive 272 each are a thermally conductive adhesive (thermal interface material)) but does not explicitly disclose where said second TIM is sandwiched between two second metal layers, and the two second metal layers are electrically floating.
Lee teaches an adhesive heat dissipation structure for a heat dissipation device comprising a phase change first thermal interface material (TIM) sandwiched between two first metal layers (Lee, see page 2 of translation, Fig. 2 see: phase change material 200 filling a gap of the porous structure 100 sandwiched between outer sealing parts formed from copper with an adhesive layer coated thereon for attaching to an electronic device). Lee teaches this heat dissipation structure provides an improved heat dissipation function (Lee, see Abstract).
Modified Lofgreen and Lee are combinable as they are both concerned with the field of thermal interface materials for integrated circuit chips.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Lofgreen in view of Lee such that the first thermal interface material (TIM) of modified Lofgreen is a phase change first thermal interface material (TIM) sandwiched between two first metal layers as taught by Lee (Lee, see page 2 of translation, Fig. 2 see: phase change material 200 filling a gap of the porous structure 100 sandwiched between outer sealing parts formed from copper with an adhesive layer coated thereon for attaching to an electronic device) or that the second TIM of modified Lofgreen is a phase change thermal interface material (TIM) sandwiched between two second metal layers as taught by Lee as Lee teaches this heat dissipation structure provides an improved heat dissipation function (Lee, see Abstract). Furthermore, as Lee teaches adhesive layers coated on the copper outer sealing parts, these two copper (first metal layers or second metal layers) are considered electrically floating.
Claims 24-27 and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al (US 2020/0395313) and further in view of Scullin (US 2011/0114146) as further evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation).
Regarding claim 24 Mallik discloses a method of forming a package structure, comprising:
providing a die having a first surface and a second surface opposite to each other ([0041], Figs. 2E-2F see: one of dies 220);
forming a first RDL structure over the first surface of the die ([0045]-[0046], Figs. 2E-2F see: either redistribution layer 251(Fig. 2E) or redistribution layer 253(Fig. 2F) formed over the bottom (first surface) of die 220);
bonding a first thermoelectric cooler over the first RDL structure ([0036], [0045]-[0046], Figs. 2E-2F see: nested component 240 (thermo-electric cooler) bonded to either redistribution layer 251(Fig. 2E) or redistribution layer 253(Fig. 2F));
forming a passive device aside the first thermoelectric cooler ([0035], [0045]-[0046], Figs. 2E-2F see: interposer 230 formed aside nested component 240 (thermo-electric cooler));
bonding a circuit substrate over the first RDL structure away from the first surface of the die through a plurality of first conductive connectors ([0042], [0069]-[0070], Figs. 2E-2F, 6 see: package substrate 671 bonded to the side of the interposers 630 (230) and nested components 640(240) opposite the dies 620(220) through package side bumps 637(237) which also connect to dies 620 and thus also to the RDL in Figs. 2E-2F), wherein the first thermoelectric cooler and the passive device are vertically sandwiched between the first RDL structure and the circuit substrate ([0042], [0069]-[0070], Figs. 2E-2F, 6 see: as the package substrate 671 is further bonded to bumps 637(237) the interposers 630 (230) and nested components 640(240) are between the package substrate 671 and either redistribution layer 251(Fig. 2E) or redistribution layer 253(Fig. 2F)); and
forming a first underfill layer to laterally encapsulate the plurality of first conductive connectors, the first thermoelectric cooler, and the passive device ([0042], [0069]-[0070], Figs. 2E-2F, 6 see: underfill material 674 laterally encapsulating package side bumps 637(237), nested components 640(240) and interposers 630 (230)). Although Mallik does not explicitly illustrate wherein the first underfill layer further extends to cover a sidewall of the first RDL structure in Fig. 6, as Fig. 6 does illustrate the underfill material 674 extending to laterally encapsulate dies 620(220) which are above where the first RDL structure is located in Figs. 2E-2F (RDL structure 251 or 253) it would have been obvious to one having ordinary skill in the art at the time of the invention to also cover a sidewall of the first RDL structure when applying an underfill material as in Fig. 6 to the embodiment of Figs. 2E-2F in order to reach the sidewall of dies 620(220) as in Fig. 6, given the first RDL structure (RDL structure 251 or 253) is located between the dies and the nested components and interposers).
Mallik does not explicitly disclose forming the first thermoelectric cooler comprises: performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate.
However, Scullin discloses a method for forming a first thermoelectric cooler (para [0026]) comprising performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate (Scullin, [0027]-[0029], Figs. 1, 3D, 4 see: providing substrate material (101), forming first regions with n-type semiconductor characteristics (113), forming second regions with p-type semiconductor characteristics (114), separated by intermediate regions 117 of the substrate material re-configured or functionalized to be a substantial electric insulator and a good thermal isolator) which is further evidenced by Strasser to be formed in silicon substrates (Strasser, see page 3 of translation, Figs. 2-4, see: thermoelectric device formed by doping body silicon layer of silicon blocks 10 with a first doping process 8 forming n-doped sections 12 and second doping process 9 forming p-doped sections 11 both separated by undoped sections 13).
Scullin discloses this method of manufacture for thermoelectric coolers reduces the process complexity, number of steps, and cost of production (paras [0021]-[0022]).
Scullin, Strasser and Mallik are combinable as they are all concerned with the field of thermoelectric device manufacture.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Scullin as evidenced by Strasser such that the method of manufacturing the first thermoelectric cooler of Mallik comprises performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate as taught by Scullin ([0027]-[0029], Figs. 1, 3D, 4 see: providing substrate material (101), forming first regions with n-type semiconductor characteristics (113), forming second regions with p-type semiconductor characteristics (114), separated by intermediate regions 117 of the substrate material re-configured or functionalized to be a substantial electric insulator and a good thermal isolator) and as further evidenced by Strasser to be formed in silicon substrates (Strasser, see page 3 of translation, Figs. 2-4, see: thermoelectric device formed by doping body silicon layer of silicon blocks 10 with a first doping process 8 forming n-doped sections 12 and second doping process 9 forming p-doped sections 11 both separated by undoped sections 13) as Scullin discloses this method of manufacture for thermoelectric coolers reduces the process complexity, number of steps, and cost of production (paras [0021]-[0022]).
Regarding claim 25 modified Mallik discloses the method of claim 24, and Scullin discloses wherein the plurality of N-type doped regions and the plurality of P-type doped regions are connected to each other in series (Scullin, [0029]-[0030], Fig. 1 see: n-type regions 113 and p-type regions 115 connected in series by conductor shunts 123 and 125), the first thermoelectric cooler is configured to form a temperature gradient across a top surface and the bottom surface of the first thermoelectric cooler when a voltage is applied across the plurality of N-type doped regions and the plurality of P- type doped regions (Scullin, [0034] see: uniwafer thermoelectric device 200 can be used for pumping thermal energy out of a subjected surface through all the functionalized n- and p-type regions coupled between the front shunts and the back shunts when an external control voltage is applied to the two leads 251 and 252).
Regarding claim 26 modified Mallik discloses the method of claim 24, further comprising: forming an encapsulant to laterally encapsulate the die, wherein the first RDL structure further extends over the encapsulant ([0038], [0045]-[0046], Figs. 1A, 2E-2F see: mold layer 122 laterally encapsulates dies 220 and RDL structure 251 or 253 extend over the mold layer).
Regarding claim 27 modified Mallik discloses the method of claim 24, wherein a vertical projection of the first thermoelectric cooler and a vertical projection of the die are overlapped to each other ([0036], [0045]-[0046], Figs. 2A, 2E-2F see: nested component 240 (thermo-electric cooler) which can be a first nested component 240A or second nested component 240B overlap the dies 220 in a thickness direction).
Regarding claim 32 Mallik discloses a method of forming a package structure, comprising:
providing a die having a first surface and a second surface opposite to each other ([0041]-[0042], Figs. 2A-2B see: one of dies 220);
forming a first thermoelectric cooler over the first surface of the die ([0036], [0041]-[0042], Figs. 2A-2B see: second nested component 240B which comprises a thermo-electric cooler over the bottom surface of one of dies 220), wherein the first thermoelectric cooler is within a perimeter of the die ([0036], [0041]-[0042], Figs. 2A-2B see: second nested component 240B within the perimeter of die 220);
forming a passive device aside the first thermoelectric cooler ([0035]-[0036], [0041]-[0042], Figs. 2A-2B see: either passive first nested component 240A or one of interposers 230 formed aside second nested component 240B (thermo-electric cooler)); and
forming a first underfill layer to laterally encapsulate the first thermoelectric cooler and the passive device, wherein the die is within a perimeter of the first underfill layer ([0069]-[0070], Fig. 6 see: underfill material 674 formed to laterally encapsulate the nested components 640 and interposers 630, where dies 620 are within a perimeter of the underfill material 674).
Mallik does not explicitly disclose forming the first thermoelectric cooler comprises: performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate.
However, Scullin discloses a method for forming a first thermoelectric cooler (para [0026]) comprising performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate (Scullin, [0027]-[0029], Figs. 1, 3D, 4 see: providing substrate material (101), forming first regions with n-type semiconductor characteristics (113), forming second regions with p-type semiconductor characteristics (114), separated by intermediate regions 117 of the substrate material re-configured or functionalized to be a substantial electric insulator and a good thermal isolator) which is further evidenced by Strasser to be formed in silicon substrates (Strasser, see page 3 of translation, Figs. 2-4, see: thermoelectric device formed by doping body silicon layer of silicon blocks 10 with a first doping process 8 forming n-doped sections 12 and second doping process 9 forming p-doped sections 11 both separated by undoped sections 13).
Scullin discloses this method of manufacture for thermoelectric coolers reduces the process complexity, number of steps, and cost of production (paras [0021]-[0022]).
Scullin, Strasser and Mallik are combinable as they are all concerned with the field of thermoelectric device manufacture.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Scullin as evidenced by Strasser such that the method of manufacturing the first thermoelectric cooler of Mallik comprises performing a first doping process on a semiconductor substrate to form a plurality of N-type doped regions in the semiconductor substrate; and performing a second doping process on the semiconductor substrate to form a plurality of P-type doped regions in the semiconductor substrate, wherein the plurality of N-type doped regions are laterally separated from the plurality of P-type doped regions by portions of the semiconductor substrate as taught by Scullin ([0027]-[0029], Figs. 1, 3D, 4 see: providing substrate material (101), forming first regions with n-type semiconductor characteristics (113), forming second regions with p-type semiconductor characteristics (114), separated by intermediate regions 117 of the substrate material re-configured or functionalized to be a substantial electric insulator and a good thermal isolator) and as further evidenced by Strasser to be formed in silicon substrates (Strasser, see page 3 of translation, Figs. 2-4, see: thermoelectric device formed by doping body silicon layer of silicon blocks 10 with a first doping process 8 forming n-doped sections 12 and second doping process 9 forming p-doped sections 11 both separated by undoped sections 13) as Scullin discloses this method of manufacture for thermoelectric coolers reduces the process complexity, number of steps, and cost of production (paras [0021]-[0022]).
Regarding claim 33 modified Mallik discloses the method of claim 32, and Scullin discloses wherein the plurality of N-type doped regions and the plurality of P-type doped regions are connected to each other in series (Scullin, [0029]-[0030], Fig. 1 see: n-type regions 113 and p-type regions 115 connected in series by conductor shunts 123 and 125), the first thermoelectric cooler is configured to form a temperature gradient across a top surface and the bottom surface of the first thermoelectric cooler when a voltage is applied across the plurality of N-type doped regions and the plurality of P- type doped regions (Scullin, [0034] see: uniwafer thermoelectric device 200 can be used for pumping thermal energy out of a subjected surface through all the functionalized n- and p-type regions coupled between the front shunts and the back shunts when an external control voltage is applied to the two leads 251 and 252).
Regarding claim 34 modified Mallik discloses the method of claim 32, wherein the passive device spans a sidewall of the die ([0035]-[0036], [0041]-[0042], Figs. 2A-2B see: passive first nested component 240A spans the sidewall of dies 220, also shown in Figs. 3A-3C and 4 with interposers 330 or 430 spanning sidewalls of dies 320 or 420).
Claims 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al (US 2020/0395313) in view of Scullin (US 2011/0114146) as evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation) as applied to claims 24-27, and 32-34 above, and further in view of Mittal et al (US 2016/0334845) and in further view of Lee et al (KR 20150007827A, reference made to attached English machine translation).
Regarding claim 28 modified Mallik discloses the method of claim 24, but does not explicitly disclose wherein the first thermoelectric cooler is bonded onto the first RDL structure by a first adhesive structure, and bonded onto the circuit substrate by a second adhesive structure, the first adhesive structure comprises a first thermal interface material (TIM) sandwiched between two first metal layers, and the two first metal layers are electrically floating.
Mittal teaches in package structures with thermoelectric coolers, the thermoelectric coolers can be adhered at its upper and lower surfaces through a first adhesive structure and a second adhesive structure (Mittal, [0038], [0046], Fig. 2 see: TEC 210 bonded at upper and lower surfaces through adhesive 270 and adhesive 272).
Mittal and Mallik are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Mittal such that the first thermoelectric cooler of Mallik is bonded onto the first RDL structure of Mallik by a first adhesive structure, and bonded onto the circuit substrate of Mallik by a second adhesive structure as taught by Mittal ([0038], [0046], Fig. 2 see: TEC 210 bonded at upper and lower surfaces through adhesive 270 and adhesive 272) as such a modification would have amounted to the use of a known thermal interface bonding material for its intended use in a known environment of a semiconductor package structure to accomplish the entirely expected result of adhering the thermoelectric cooler to device interfaces for cooling while providing a thermally conductive interface for heat transfer.
Mittal discloses where the first adhesive structure comprises a first thermal interface material (TIM) (Mittal, [0038], [0046], Fig. 2 see: adhesive 270 and adhesive 272 each are a thermally conductive adhesive (thermal interface material)) but does not explicitly disclose where said first TIM is sandwiched between two first metal layers, and the two first metal layers are electrically floating.
Lee teaches an adhesive heat dissipation structure for a heat dissipation device comprising a phase change first thermal interface material (TIM) sandwiched between two first metal layers (Lee, see page 2 of translation, Fig. 2 see: phase change material 200 filling a gap of the porous structure 100 sandwiched between outer sealing parts formed from copper with an adhesive layer coated thereon for attaching to an electronic device). Lee teaches this heat dissipation structure provides an improved heat dissipation function (Lee, see Abstract).
Modified Mallik and Lee are combinable as they are both concerned with the field of thermal interface materials for integrated circuit chips.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Lee such that the first thermal interface material (TIM) of modified Mallik is a phase change first thermal interface material (TIM) sandwiched between two first metal layers as taught by Lee (Lee, see page 2 of translation, Fig. 2 see: phase change material 200 filling a gap of the porous structure 100 sandwiched between outer sealing parts formed from copper with an adhesive layer coated thereon for attaching to an electronic device) as Lee teaches this heat dissipation structure provides an improved heat dissipation function (Lee, see Abstract). Furthermore, as Lee teaches adhesive layers coated on the copper outer sealing parts, these two copper (first metal layers) are considered electrically floating.
Regarding claim 29 modified Mallik discloses the method of claim 28, and Mittal discloses wherein the second adhesive structure comprises a second TIM (Mittal, [0038], [0046], Fig. 2 see: adhesive 270 and adhesive 272 each are a thermally conductive adhesive (thermal interface material)) but does not explicitly disclose the second TIM is sandwiched between two second metal layers, and the two second metal layers are electrically floating, however as recited in claim 28 above it would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Lee such that the second thermal interface material (TIM) of modified Mallik is a phase change second thermal interface material (TIM) sandwiched between two second metal layers as taught by Lee (Lee, see page 2 of translation, Fig. 2 see: phase change material 200 filling a gap of the porous structure 100 sandwiched between outer sealing parts formed from copper with an adhesive layer coated thereon for attaching to an electronic device) as Lee teaches this heat dissipation structure provides an improved heat dissipation function (Lee, see Abstract). Furthermore, as Lee teaches adhesive layers coated on the copper outer sealing parts, these two copper (second metal layers) are considered electrically floating.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al (US 2020/0395313) in view of Scullin (US 2011/0114146) as evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation) as applied to claims 24-27, and 32-34 above, and further in view of Yu’807 (US 2017/0345807) and further in view of Huang et al (US 2021/0013191).
Regarding claim 30 modified Mallik discloses the method of claim 24, but does not explicitly disclose further comprising: forming a second RDL structure over the second surface of the die; bonding a second package component to the second RDL structure through a plurality of second conductive connectors; and forming a second underfill layer to laterally encapsulate the plurality of second conductive connectors, and continuously extend between the plurality of second conductive connectors, wherein the second underfill layer further extends to cover a lower sidewall of the second package component.
Yu’807 discloses a package structure comprising forming a second RDL structure over the second surface of the die; bonding a second package component to the second RDL structure through a plurality of second conductive connectors; and forming a second underfill layer to laterally encapsulate the plurality of second conductive connectors, and continuously extend between the plurality of second conductive connectors (Yu’807, [0023]-[0024], [0034], Figs. 10-11A see: forming RDLs 52 in dielectric layers 50 over device die 58 and bonding package structure 200 to the RDLs 52 through the solder regions 84 laterally encapsulated by underfill 86). Yu’807 discloses this allows formation of a multi-stack package of additional device dies (Yu’807, [0010]).
Mallik and Yu’807 are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Yu’807 such that the method further comprises forming a second RDL structure over the second surface of the die of Mallik; bonding a second package component to the second RDL structure through a plurality of second conductive connectors; and forming a second underfill layer to laterally encapsulate the plurality of second conductive connectors, and continuously extend between the plurality of second conductive connectors as in Yu’807 ([0023]-[0024], [0034], Figs. 10-11A see: forming RDLs 52 in dielectric layers 50 over device die 58 and bonding package structure 200 to the RDLs 52 through the solder regions 84 laterally encapsulated by underfill 86) as Yu’807 discloses this allows formation of a multi-stack package of additional device dies (Yu’807, [0010]).
Modified Mallik does not explicitly disclose where the second underfill layer further extends to cover a lower sidewall of the second package component.
However Huang discloses where the underfill layer between two package components further extends to cover a lower sidewall of the second package component (Huang, [0042]-[0043] Fig. 1H see: underfill layer 206 continuously extending between conductive connectors 204 and passive device 120 and further extending to cover a lower sidewall of upper package 10c).
Huang and modified Mallik are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of modified Mallik in view of Huang such that second underfill layer of modified Mallik further extends to cover a lower sidewall of the second package component of modified Mallik as in Huang (Huang, [0042]-[0043] Fig. 1H see: underfill layer 206 extending to cover a lower sidewall of upper package 10c) as such a modification would have amounted to use of a known underfill layer structure in the known environment of a package structure for its intended use to accomplish the entirely expected result of providing mechanical reinforcement to the interconnect layer.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al (US 2020/0395313) in view of Scullin (US 2011/0114146) as evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation) in view of Yu’807 (US 2017/0345807) in view of Huang et al (US 2021/0013191) as applied to claims 24-27, 30, and 32-34 above, and further in view of Mittal et al (US 2016/0334845).
Regarding claim 31 modified Mallik discloses the method of claim 30, but does not explicitly disclose further comprising: forming a second thermoelectric cooler laterally between the plurality of second conductive connectors, wherein the second thermoelectric cooler is directly over the die.
Mittal teaches package structures can include multiple thermoelectric coolers (Fig. 21 see: TECs 2150, 2110, 2112) including a thermoelectric cooler laterally between the plurality of second conductive connectors between stacked package structures directly over the die of the lower package (Mittal, [0140]-[0147], Fig. 21, see: either of TECs 2110 or 2112 provided directly over first die 2122 or second die 2123 between conductive connections mounting first package 2102 to second package 2104). Mittal teaches these thermoelectric coolers can be bidirectional to dynamically dissipate heat back and forth between the stacked packages (paras [0143]-[0147]).
Mittal and modified Mallik are combinable as they are both concerned with the field of semiconductor package structures.
As such, it would have been obvious to one having ordinary skill in the art at the time of the invention to further modify the method of modified Mallik in view of Mittal to further comprise forming a second thermoelectric cooler laterally between the plurality of second conductive connectors, wherein the second thermoelectric cooler is directly over the die as in Mittal (Mittal, [0140]-[0147], Fig. 21, see: either of TECs 2110 or 2112 provided directly over first die 2122 or second die 2123 between conductive connections mounting first package 2102 to second package 2104) as Mittal teaches these thermoelectric coolers can be bidirectional to dynamically dissipate heat back and forth between the stacked packages (paras [0143]-[0147]).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al (US 2020/0395313) in view of Scullin (US 2011/0114146) as evidenced by Strasser et al (DE 10004390A1, reference made to attached English machine translation) as applied to claims 24-27, and 32-34 above, and further in view of Lee’140 (US 2006/0001140).
Regarding claim 35 Mallik discloses the method of claim 32, but does not explicitly disclose further comprising: forming a second thermoelectric cooler over the second surface of the die, wherein the second thermoelectric cooler is within the perimeter of the die.
Lee’140 discloses forming a semiconductor chip package further comprising forming a second thermoelectric cooler over the second surface of the die, wherein the second thermoelectric cooler is within the perimeter of the die (Lee’140, [0063]-[0065], Fig. 7 see: overlap of N-type and P-type material plates 252b and 253b forming a second thermoelectric cooler 251b inside the perimeter overlap of chips 11, 13, 15). Lee’140 teaches this arrangement can provide cooling for multi-stacked semiconductor chips (Lee’140, [0063]-[0065]).
Mallik and Lee’140 are combinable as they are both concerned with the field of semiconductor package structures.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the method of Mallik in view of Lee’140 such that the method further comprises forming a second thermoelectric cooler over the second surface of the die, wherein the second thermoelectric cooler is within the perimeter of the die as in Lee’140 ([0063]-[0065], Fig. 7 see: overlap of N-type and P-type material plates 252b and 253b forming a second thermoelectric cooler 251b inside the perimeter overlap of chips 11, 13, 15) as Lee’140 teaches this arrangement can provide cooling for multi-stacked semiconductor chips (Lee’140, [0063]-[0065]).
Response to Arguments
Applicant’s arguments with respect to claims 10-14 and 21-35 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW J GOLDEN whose telephone number is (571)270-7935. The examiner can normally be reached 11am-8pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Barton can be reached at 571-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
ANDREW J. GOLDEN
Primary Examiner
Art Unit 1726
/ANDREW J GOLDEN/Primary Examiner, Art Unit 1726
Prosecution Insights