DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending of which claims 1, 9 and 16 are in independent form.
Claims 1-20 are rejected on the ground of nonstatutory double patenting.
Claims 1-20 are rejected under 35 U.S.C. 103.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the Double Patenting Rejection:
Applicant’s Arguments that the amended claims overcome the non-statutory double patenting rejection has been considered by not persuasive. Although, claims 1, 9 and 16 now additionally recite “dicing the semiconductor wafer along scribe lines when the semiconductor process has been completed, so as to obtain dies”, the reference claims already recite substantially the same semiconductor wafer inspection and processing method. The added dicing limitation does not render the claims patentably distinct because Keto et al. (US 20120018854 A1) evidence that it was known to dice a processed semiconductor wafer along dicing lines between semiconductor device portions to separate the wafer into individual semiconductor devices. Accordingly, it would have been obvious to perform the known wafer singulation step following completion of the semiconductor processing recites by reference claims to obtain individual dies, and therefore the obviousness type double patenting rejection is maintained.
Regarding the 35 USC 101:
Applicant’s arguments, see “Remarks”, filed 7/6/2026, with respect to 35 USC 101 have been fully considered and are persuasive. The 35 USC 101 of claims 1-20 has been withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12080042, and claims 1-20 of U.S. Patent No. US 12374076 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rose; Geordie et al. (US 20150006443 A1) [Rose] in view of Gu; Kunlong et al. (US 20150169754 A1) [Gu] in view of Mitarai; Yusuke (US 20180218487 A1) [Mitarai] in view of Kato; Takanori et al. (US 20120018854 A1) [Kato].
Regarding claims 1 and 16, Rose discloses, a method for processing a semiconductor wafer (discloses a method for processing image data using sparse coding and dictionary learning ¶ [0559]-[0571]), comprising:
encoding patches with a set of weightings to obtain an encoding matrix (image patches…each has an encoding (dividing images into patches) ¶ [0578]; W matrices are the weights of dictionary atoms… representation of the input image (applying sparse coding using dictionary atoms and weights (W matrices)) ¶ [0359]; concatenated…into matrix (forming a data matrix/encoded representation) ¶ [0494]);
wherein encoding the patches with the set of weightings to obtain the encoding matrix (image patches…each has an encoding (dividing images into patches) ¶ [0578]; W matrices are the weights of dictionary atoms… representation of the input image (applying sparse coding using dictionary atoms and weights (W matrices)) ¶ [0359]; concatenated…into matrix (forming a data matrix/encoded representation) ¶ [0494]) further comprises:
encoding a first set of the patches with a first set of weightings to obtain a first intermediate matrix (encoding patches into vector/matrix representation ¶ [0494], [0578]);
encoding a second set of the patches with a second set of weightings to obtain a second intermediate matrix, wherein the second set of weightings is obtained by modifying a plurality of bases of a sparsity-based dictionary according to the first intermediate matrix (dictionary learning – iterative updating of weights/bases ¶ [0564]-[0570], [0359]);
[encoding a third set of the patches with a third set of weightings to obtain a third intermediate matrix], wherein the [third set of weightings] is obtained by modifying the bases of the sparsity-based dictionary [according to the second intermediate matrix] (iterative learning over multiple passes of data ¶ [0568]-[0571]); and
assigning the third intermediate matrix as the encoding matrix (final encoded representation is used for downstream processing ¶ [0587]).
However, Rose does not explicitly facilitate, retrieving images corresponding to a query image according to the encoding matrix, generating an inspection result according to the retrieved images.
Gu discloses, retrieving images corresponding to a query image according to the encoding matrix (receiving…a search query and … image…responsive to the search query (receiving and search query and corresponding images)… computing similarity and ranking images (relevance score) [Abstract]; representing images using vectors ¶ [0055]-[0056]);
generating an inspection result according to the retrieved images (generating relevance score/ranking results based on the retrieved images [Abstract], ¶ [0074]);
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Gu’s system would have allowed Rose to facilitate retrieving images corresponding to a query image according to the encoding matrix, generating an inspection result according to the retrieved images. The motivation to combine is apparent in the Rose’s reference, because there is a need to improve analyzing image search result relevance.
However, however neither Rose nor Gu explicitly facilitate, performing a semiconductor process on the semiconductor wafer when the inspection result is normal; encoding a third set of the patches with a third set of weightings to obtain a third intermediate matrix… third set of weightings… according to the second intermediate matrix.
Mitarai discloses, performing a semiconductor process on the semiconductor wafer when the inspection result is normal (generates a model of normal patterns,…performs surface inspection based on captured image,...evaluated whether data belongs to normal category ¶ [0030], patch based inspection process ¶ [0056], process continues after evaluation ¶ [0167]);
encoding a third set of the patches with a third set of weightings to obtain a third intermediate matrix (auto-encoder…encodes an input patch ¶ [0167], inspection patches are generated/processed ¶ [0056]), third set of weightings… according to the second intermediate matrix (plurality of layers…hierarchical processing, encoding performed in order layers, output of one layer is used for the input to next ¶ [0167]; examiner specifies that Mitarai teaches dependency between intermediate matrices).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Mitarai’s system would have allowed Rose and Gu to facilitate performing a semiconductor process on the semiconductor wafer when the inspection result is normal; encoding a third set of the patches with a third set of weightings to obtain a third intermediate matrix… third set of weightings… according to the second intermediate matrix. The motivation to combine is apparent in the Rose and Gu’s reference, because there is a need for appropriate model used for evaluating the category of data.
However, neither one of Rose, Gu, or Mitarai explicitly facilitates dicing the semiconductor wafer along scribe lines when the semiconductor process has been completed, so as to obtain dies.
Kato discloses, dicing the semiconductor wafer (Specifically, the semiconductor wafer is divided into individual semiconductor device portions and the semiconductor wafer is transferred on the dicing sheet serving as a supporting sheet ¶ [0048], [0061], [0064], [0082]; then dicing the semiconductor wafer in a lattice pattern to separate the individual semiconductor device portions from one another ¶ [0004]) along scribe lines ( the grooves 44 are formed between the semiconductor device portions 24 by moving a blade 26 rotating in high speed along the dicing lines 27 defined on the semiconductor wafer 22 ¶ [0053]; dicing the semiconductor wafer from the side of the first main surface along border lines between the semiconductor device portions to form grooves each having a depth smaller than a thickness of the semiconductor wafer ¶ [0020]; With reference to Part (A) of FIG. 2, a large number of (some hundreds of) semiconductor device portions 24 arranged in a matrix are formed in the semiconductor wafer 22. Each of the semiconductor device portions 24 is a portion to be a single semiconductor device. Dicing lines 27 in a lattice pattern are defined between the semiconductor device portions 24. In the later step, the semiconductor wafer 22 is separated into individual semiconductor devices along the dicing lines 27 ¶ [0050], [0053], [0054]) when the semiconductor process has been completed (In the above description, the laser marking is performed on the semiconductor wafer 22 separated into the semiconductor device portions 24 in the laser marking step. Instead, the laser marking may be performed on the semiconductor wafer 22 before being separated. In this case, with reference to FIG. 8, the unseparated semiconductor wafer 22 is attached on the upper surface of the dicing sheet 21 and the laser is applied thereto from below. By the dicing after the laser marking, the semiconductor wafer 22 is separated into individual semiconductor device portions ¶ [0082]), so as to obtain dies (Specifically, the semiconductor wafer is divided into individual semiconductor device portions and the semiconductor wafer is transferred on the dicing sheet serving as a supporting sheet ¶ [0048], [0061], [0064], [0082]; then dicing the semiconductor wafer in a lattice pattern to separate the individual semiconductor device portions from one another ¶ [0004]).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Kato’s system would have allowed Rose, Gu, and Mitarai to facilitate dicing the semiconductor wafer along scribe lines when the semiconductor process has been completed, so as to obtain dies. The motivation to combine is apparent in the Rose, Gu and Mitarai’s reference, because there is a need for improved manufacturing a semiconductor device including a marking on a main surface of the semiconductor device from which a semiconductor material is exposed.
Regarding claims 2, 10 and 17, the combination of Rose, Gu, Mitarai, and Kato discloses, extracting the patches from the query image; selecting the bases from the sparsity-based dictionary, wherein each of the bases forms a column vector corresponding to an individual column of the query image (Rose: extracting image patches/regions ¶ [0628], dictionary based sparse representation,…bases vectors forming representation space ¶ [0359]. Examiner specifies that bases (dictionary atoms) are interpreted as column vectors).
Regarding claims 3 and 18, the combination of Rose, Gu, Mitarai, and Kato discloses, wherein extracting the patches from the query image further comprises: dividing the query image into a plurality of row vectors, wherein each of the row vectors corresponds to an individual patch (Rose: image partitioning into patches,… vectorized representation of image portions ¶ [0628]; examiner specifies that row vectors are the same as patch vectors, and each patch has a individual vector representation).
Regarding claims 4, 11 and 19, the combination of Rose, Gu, Mitarai, and Kato discloses, calculating a plurality of projection values to obtain projections for the row vectors on the column vectors; and obtaining the set of weightings according to the projections, wherein the projection having a maximum projection value is obtained (Rose: sparse coding using dictionary atoms (weights determining relative to dictionary atoms), coefficient/weigh selection based on representation ¶ [0359]).
Regarding claims 5 and 12, the combination of Rose, Gu, Mitarai, and Kato discloses, wherein obtaining the set of weightings according to the projections further comprises: normalizing the non-zero weightings (Rose: encoding produces structure vectors with controlled magnitude (normalized encoded vectors) ¶ [0059]) within the set of weightings to a length (Gu: relevance score…threshold comparison ¶ [0087]).
Regarding claims 6 and 13, the combination of Rose, Gu, Mitarai, and Kato discloses, increasing value of the bases of the sparsity-based dictionary corresponding to the projection having the maximum projection value; and decreasing values of the bases of the sparsity-based dictionary corresponding to the projections without the maximum projection value (Rose: W matrices…weights…updated (updating dictionary atoms/weights ¶ [0359]. Iterative learning adjusts contribution of atoms ¶ [0568]-[0571]. Increasing/decreasing = weight updates to dictionary bases).
Regarding claims 7, 15, and 20, the combination of Rose, Gu, Mitarai, and Kato discloses, wherein the patches have the same size (Rose: same/fixed image patch size… ¶ [0628]).
Regarding claims 8 and 14, the combination of Rose, Gu, Mitarai, and Kato discloses, wherein each of the non-zero weightings within the set of weightings has a weighting value equal to or less than 1 (Gu: compared to threshold…meet/exceeds threshold ¶ [0087]-[0090]).
Regarding claim 9, the combination of Rose, Gu, Mitarai, and Kato clearly show a method for performing the process for the method in claims 1 and 3. Therefore, the rejections of claims 1 and 3 applies to claim 9.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD S ROSTAMI whose telephone number is (571)270-1980. The examiner can normally be reached Mon-Fri From 9 a.m. to 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Boris Gorney can be reached at (571)270-5626. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
9/19/2026
/MOHAMMAD S ROSTAMI/Primary Examiner, Art Unit 2154
Prosecution Insights