DETAILED ACTION
Note
This Office Action vacates and replaces the previous Office Action in its entirety and cancels the previous Office Action dated on 02/18/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 2
1. Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fish (US 2007/0236430).
1. (Canceled)
As to claim 2, Fish teaches a display apparatus comprising a pixel comprising: a first transistor (addressing transistor 16, fig. 5), a second transistor ( a discharge transistor 36, fig. 5), a third transistor (Turning on transistor 34, fig. 5), a fourth transistor (drive transistor 22, fig. 5), a capacitor (discharge capacitor 40, fig. 5), and a light-emitting device ( display element 2, fig. 5), wherein one of a source and a drain of the first transistor is electrically connected to a source line ( fig. 5 illustrates that addressing transistor 16 is coupled to the data line), wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor (see fig. 5), wherein a gate of the first transistor is electrically connected to a gate line (see the gate of the addressing transistor 16, fig. 5), wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor (Turning on transistor 34, fig. 5), wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the fourth transistor (drive transistor 22, fig. 5), wherein the other of a source and a drain of the second transistor is electrically connected to a first wiring ( power line 26, fig. 5), wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring (ground, fig. 5), wherein a gate of the third transistor is electrically connected to a third wiring (see the gate of Turning on transistor 34, fig. 5), wherein one of a source and a drain of the fourth transistor is electrically connected to the light-emitting device (display element 2, fig. 5), wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth wiring (power line 26, fig. 5), wherein one electrode of the capacitor is electrically connected to the gate of the second transistor (a discharge transistor 36, fig. 5), and wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor (see fig. 5).
As to claim 8, Fish teaches a display apparatus comprising a pixel comprising: a first transistor (addressing transistor 16, fig. 5), a second transistor ( a discharge transistor 36, fig. 5), a third transistor (drive transistor 22, fig. 5), and a light-emitting device (display element 2, fig. 5), wherein one of a source and a drain of the first transistor (addressing transistor 16, fig. 5) is electrically connected to a gate of the second transistor (a discharge transistor 36, fig. 5), wherein one of a source and a drain of the second transistor (a discharge transistor 36, fig. 5) is electrically connected to a gate of the third transistor (drive transistor 22, fig. 5), and wherein one of a source and a drain of the third transistor is electrically connected to the light-emitting device (display element 2, fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fish (US 2007/0236430) in view of Yamazaki et al (US 2018/0240421).
As to claim 3, Fish does not expressly disclose wherein the second transistor comprises silicon in a channel formation region.
However, Yamazaki teaches the display apparatus wherein the transistor comprises silicon in a channel formation region ([0177] amorphous silicon can be used as the semiconductor material used for the transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fish to teach, transistor comprises silicon in a channel formation region, as suggested by Yamazaki. The motivation would have been in order to provide “a high-resolution display device” ([0009]).
As to claim 4, Fish does not expressly disclose wherein the first transistor comprises a metal oxide in a channel formation region
However, Yamazaki teaches the display apparatus wherein the transistor comprises a metal oxide in a channel formation region ([0179] an oxide semiconductor, which is a kind of a metal oxide, can be used as the semiconductor material used for the transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fish to teach, transistor comprises a metal oxide in a channel formation region, as suggested by Yamazaki. The motivation would have been in order to provide “a high-resolution display device” ([0009]).
3. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fish (US 2007/0236430) in view of Xi et al (US 2021/0193026).
As to claim 5, Fish a display apparatus comprising a pixel comprising: a first transistor (addressing transistor 16, fig. 5), a second transistor (a discharge transistor 36, fig. 5), a third transistor (Turning on transistor 34, fig. 5), a fourth transistor (drive transistor 22, fig. 5), a capacitor (discharge capacitor 40, fig. 5), and a light-emitting device (display element 2, fig. 5), wherein one of a source and a drain of the first transistor is electrically connected to a source line (fig. 5 illustrates that addressing transistor 16 is coupled to the data line), wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor (see fig. 5), wherein a gate of the first transistor is electrically connected to a gate line (see the gate of the addressing transistor 16, fig. 5), wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor (Turning on transistor 34, fig. 5), wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the fourth transistor (drive transistor 22, fig. 5), wherein a gate of the third transistor is electrically connected to a wiring (see the gate of Turning on transistor 34, fig. 5), wherein one of a source and a drain of the fourth transistor is electrically connected to the light-emitting device (display element 2, fig. 5), wherein one electrode of the capacitor (capacitor 40, fig. 5) is electrically connected to the gate of the second transistor (transistor 36, fig. 5), wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor (transistor 36, fig. 5)
Fish does not teach supplying a ramp wave to the wiring as claimed.
However, Xi teaches wherein a ramp wave is supplied to the wiring ([0058] timing control signal TCS is a descending ramp wave, fig. 12A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fish to teach, supplying a ramp wave to the wiring, as suggested by Xi. The motivation would have been in order to improve “a light-emitting efficiency of an LED” ([0005]).
4. Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fish (US 2007/0236430) in view of Xi et al (US 2021/0193026) and further in view of Yamazaki et al (US 2018/0240421).
As to claim 6, Fish in view of Xi do not expressly disclose wherein the second transistor comprises silicon in a channel formation region.
However, Yamazaki teaches the display apparatus wherein the transistor comprises silicon in a channel formation region ([0177] amorphous silicon can be used as the semiconductor material used for the transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fish in view of Xi to teach, transistor comprises silicon in a channel formation region, as suggested by Yamazaki. The motivation would have been in order to provide “a high-resolution display device” ([0009]).
As to claim 7, Fish in view of Xi do not expressly disclose wherein the first transistor comprises a metal oxide in a channel formation region
However, Yamazaki teaches the display apparatus wherein the transistor comprises a metal oxide in a channel formation region ([0179] an oxide semiconductor, which is a kind of a metal oxide, can be used as the semiconductor material used for the transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fish in view of Xi to teach, transistor comprises a metal oxide in a channel formation region, as suggested by Yamazaki. The motivation would have been in order to provide “a high-resolution display device” ([0009]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628