Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Figure 15 with corresponding claims 1-6 and 12 in the reply filed on 4-30-2026 is acknowledged. Restriction is made final. All other non-elected claims withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, claim 1 requires: “a plurality of insulating patterns on the plurality of conductive lines in the second direction and having lengthwise directions in the first direction”. It is unclear as to whether the insulating pattern or the conductive lines are in the second direction. As best understood and for purposes of Examination it will be interpreted as the conductive lines as this most closely aligns with the elected Figure 15 showing CL in the Y-direction and IP in the X-direction which is decidedly the intended directions as found in at least paragraphs 95 and 97 in the instant published specification. Dependent claims inherit this issue.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsubata et al. (US App. 20090091671 hereinafter referred to as “Tsu”) in view of Kim et al. (US App. 20200235190)
In regard to Tsu teaches a display apparatus (See at least Abstract) comprising: a substrate having a display area (see Figs. 1, 18, and 19, display region) and another area (see Fig. 1, non-display region) of the display area; a plurality of conductive lines on one side of the another area in a first direction and extending in a second direction crossing the first direction (see Fig. 18 and 19, 50a and 50b are extending in the y-axis); and a plurality of insulating patterns on the plurality of conductive lines in the second direction and having lengthwise directions in the first direction (see Fig. 19, 71a and 71b overlap 50a and 50b), wherein, in a plan view, the plurality of insulating patterns at least partially overlap some of the plurality of conductive lines (see Fig. 19, 71a and 71b overlap 50a and 50b).
Tsu is not relied upon to teach the another area is a peripheral area at a periphery.
However, Kim teaches the another area is a peripheral area at a periphery (see Fig. 1).
It would have been obvious to a person of ordinary skill in the art to modify the area of Tsu to be in the periphery of Kim to increase the display quality of the display (see Para. 3-5). Examiner also notes Tsu discloses the base product/process of a non-display area while Kim teaches the known technique of periphery area so as to yield predictable results of a non-display in the periphery in the device of Tsu.
In regard to claim 6, Tsu teaches a display apparatus (see at least Abstract) comprising: a substrate having a display area and another area (see Fig. 1, non-display region) of the display area; a first conductive line and a second conductive line on one side of the another area in a first direction and extending in a second direction crossing the first direction (see Fig. 18 and 19, 50a and 50b are extending in the y-axis);and a first insulating line between the first conductive line and the second conductive line and extending in the second direction (see Fig. 19, 71a and 71b overlap 50a and 50b), wherein opposing edges of the first insulating line that extend parallel to the second direction are between the first conductive line and the second conductive line (see Fig. 19, 71a and 71b overlap 50a and 50b).
Tsu is not relied upon to teach the another area is a peripheral area at a periphery.
However, Kim teaches the another area is a peripheral area at a periphery (see Fig. 1).
It would have been obvious to a person of ordinary skill in the art to modify the area of Tsu to be in the periphery of Kim to increase the display quality of the display (see Para. 3-5). Examiner also notes Tsu discloses the base product/process of a non-display area while Kim teaches the known technique of periphery area so as to yield predictable results of a non-display in the periphery in the device of Tsu.
Claim(s) 2, 3, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsubata et al. (US App. 20090091671 hereinafter referred to as “Tsu”) in view of Kim et al. (US App. 20200235190) in further view of Park et al. (US App. 20200219960).
Regarding claim 2, Tsu in view of Kim teaches all the limitations of claim 1.
Tsu and Kim are not relied upon to teach wherein each of the some of the plurality of conductive lines comprises a plurality of lower conductive lines spaced apart from each other in the second direction and an upper conductive line extending in the second direction and overlapping the plurality of lower conductive lines, and a number of the plurality of lower conductive lines of each of the some of the plurality of conductive lines between insulating patterns that are adjacent to each other in the second direction from among the plurality of insulating patterns, is k (where, k is a natural number).
However, Park teaches wherein each of the some of the plurality of conductive lines comprises a plurality of lower conductive lines spaced apart from each other in the second direction and an upper conductive line extending in the second direction and overlapping the plurality of lower conductive lines (see at least Figs. 8 and 15 with CLK4b and CLK4G as upper and lower extending in the y-direction with insulation between them), and a number of the plurality of lower conductive lines of each of the some of the plurality of conductive lines between insulating patterns that are adjacent to each other in the second direction from among the plurality of insulating patterns, is k (where, k is a natural number) (see at least Figs. 8 and 15 with CLK4b and CLK4G as upper and lower extending in the y-direction with insulation between them).
It would have been obvious to a person of ordinary skill in the art to modify the area of Tsu to be in the periphery of Kim with the upper and lower lines of Park
to reduce size of the peripheral area of the display (see Para. 4). Examiner also notes Tsu and Kim discloses the base product/process of a non-display periphery area while Park teaches the known technique of stacked lines so as to yield predictable results of a more densely wired non-display area in the periphery in the device of Tsu.
Regarding claim 3, Tsu in view of Kim teaches all the limitations of claim 1.
Tsu further teaches and the plurality of insulating patterns are alternately arranged in the second direction (see Fig. 19 where insulating film is alternating around scan section 16).
Tsu and Kim are not relied upon to teach wherein each of the some of the plurality of conductive lines comprises a plurality of lower conductive lines spaced apart from each other in the second direction and an upper conductive line extending in the second direction and overlapping the plurality of lower conductive lines, andthe plurality of lower conductive lines of each of the some of the plurality of conductive lines.
However, Park teaches wherein each of the some of the plurality of conductive lines comprises a plurality of lower conductive lines spaced apart from each other in the second direction and an upper conductive line extending in the second direction and overlapping the plurality of lower conductive lines (see at least Figs. 8 and 15 with CLK4b and CLK4G as upper and lower extending in the y-direction), and the plurality of lower conductive lines of each of the some of the plurality of conductive lines (see at least Figs. 8 and 15 with CLK4b and CLK4G as upper and lower extending in the y-direction with insulation between them).
It would have been obvious to a person of ordinary skill in the art to modify the area of Tsu to be in the periphery of Kim with the upper and lower lines of Park
to reduce size of the peripheral area of the display (see Para. 4). Examiner also notes Tsu and Kim discloses the base product/process of a non-display periphery area while Park teaches the known technique of stacked lines so as to yield predictable results of a more densely wired non-display area in the periphery in the device of Tsu.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsubata et al. (US App. 20090091671 hereinafter referred to as “Tsu”) in view of Kim et al. (US App. 20200235190) in further view of Lee et al. (US App. 20230094280).
Regarding claim 4, Tsu in view of Kim teaches all the limitations of claim 1.
Tsu further teaches further comprising a plurality of pixels in the display area (See Fig. 1) while Kim further teaches clock signals (See Para. 47). It would have been obvious to a person of ordinary skill in the art to modify the signals of Tsu clocks of Kim to increase the display quality of the display (see Para. 3-5).
Tsu and Kim are not relied upon to teach wherein each of the plurality of pixels comprises: a light-emitting diode comprising an anode and a cathode; a driving transistor configured to control a size of a driving current flowing to the light-emitting diode; a scan transistor configured to transmit a data voltage to a gate of the driving transistor in response to a scan signal; and a sensing transistor configured to transmit a sensing voltage or an initialization voltage to the anode of the light-emitting diode in response to a sensing signal, wherein the scan signals and the sensing signals are configured to be respectively output in response to scan signals and sensing clock signals transmitted through the plurality of conductive lines.
However, Lee teaches wherein each of the plurality of pixels comprises: a light-emitting diode comprising an anode and a cathode (see Fig. 1, EL); a driving transistor configured to control a size of a driving current flowing to the light-emitting diode (see Fig. 1, DT to EL); a scan transistor (T1) configured to transmit a data voltage (Vdata) to a gate of the driving transistor in response to a scan signal (SCAN); and a sensing transistor (T3) configured to transmit a sensing voltage or an initialization voltage to the anode of the light-emitting diode in response to a sensing signal (Vref to anode using SENSE on gate), wherein the scan signals and the sensing signals are configured to be respectively output in response to scan signals and sensing signals transmitted through the plurality of conductive lines (SCAN and SENSE are to respective gates).
It would have been obvious to a person of ordinary skill in the art to modify the area of Tsu to be in the periphery of Kim with the sensing of Lee to reduce flicker (See Para. 4).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsubata et al. (US App. 20090091671 hereinafter referred to as “Tsu”) in view of Kim et al. (US App. 20200235190) in further view of Chae et al. (US App. 20180045866).
Regarding claim 5, Tsu in view of Kim teaches all the limitations of claim 1.
Tsu further teaches and Kim are not relied upon to teach a first light-emitting diode, a second light-emitting diode, and a third light- emitting diode, in the display area and comprising a first color emission layer; a second-color quantum dot layer and a third-color quantum dot layer respectively on the second light-emitting diode and the third light-emitting diode; a penetration layer on the first light-emitting diode; and a first-color color filter layer, a second-color color filter layer, and a third-color color filter layer respectively arranged on the penetration layer, the second-color quantum dot layer, and the third-color quantum dot layer.
However, Chae teaches a first light-emitting diode, a second light-emitting diode, and a third light- emitting diode (see Fig. 8, RGB OLEDs), in the display area and comprising a first color emission layer (Para. 115 emission layer); a second-color quantum dot layer and a third-color quantum dot layer respectively on the second light-emitting diode and the third light-emitting diode (See at least Para. 12 and 44 quantum dot for each color); a penetration layer on the first light-emitting diode (see Para. 77 penetration layer); and a first-color color filter layer, a second-color color filter layer, and a third-color color filter layer respectively arranged on the penetration layer, the second-color quantum dot layer, and the third-color quantum dot layer (See Para. 9 and 49-51 color filter layer).
It would have been obvious to a person of ordinary skill in the art to modify the area of Tsu to be in the periphery of Kim with the quantum dot pixels of Chae to reproduce color properly (see Para. 6). Examiner also notes Tsu and Kim discloses the base product/process of insulating layers on wiring lines in a peripherary while Chae teaches the known technique of quantum dot pixels in a display to yield predictable results for a quantum dot display in the display of Tsu and Ohi.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes: Liu et al. (US App. 20230298509) and Ogasawara et al. (US Pat. 8780311).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW YEUNG whose telephone number is (571)272-4115. The examiner can normally be reached M-F 9am-5pm EST.
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/MATTHEW YEUNG/Primary Examiner, Art Unit 2625
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