DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 5-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
a) regarding claim 3:
The limitation, “the master feedback circuit is implemented by the second clocked CMOS inverter,” fails to comply with the written description requirement. Claim 1 states, “a slave latch, coupled to the output terminal of the multiplexer through a second clock CMOS inverter”. Therefore the claimed “second clock CMOS inverter” corresponds to element 130 in Figure 1B. There is no description in the specification of “the master feedback circuit” being implemented by element 130.
b) regarding claims 6 and 7:
The limitations, “the first N-type transistor is formed on a second intersection region between a second OD region and the first polysilicon in the layout,” from claim 6 and “the first N-type transistor is formed on a fourth intersection region between the second OD region and a second portion of the second polysilicon,” fail to comply with the written description requirement. There is no description in the specification of the claimed “the first N-type transistor” (corresponding to N01 in Figure 1B as defined in claim 5) being formed in two different places. Paragraph [0035] of the specification states, “Specifically, the transistor P01 is formed on an intersection region 230 between the upper OD region 201 and the corresponding polysilicon 202, and the transistor PR01 is formed on an intersection region 232 between the lower OD region 201 and the corresponding polysilicon 202…The transistor N01 is formed on an intersection region 236 between the lower OD region 202 and a bottom portion of the corresponding polysilicon 202.” Thus it appears “the first N-type transistor” of claim 6 should correspond to the leakage free dummy cell PR01.
c) regarding claims 5 and 8-10:
The claims are rejected based on their dependence from claim 3.
d) regarding claim 11:
The limitations, “a slave data circuit, configured to receive the input data signal from an output terminal of the first clocked CMOS inverter, and to generate a second signal; and a slave feedback circuit, configured to feed the second signal back to the output terminal of the first clocked CMOS inverter,” fail to comply with the written description requirement. Claim 1 states, “a master latch…which comprises a first inverter and a first clocked CMOS (complementary metal oxide semiconductor) inverter”. Therefore the claimed “first clocked CMOS inverter” corresponds to element 1043 in Figure 1B. There is no description in specification of “a slave data circuit” receiving a signal from element 1043, or of “a slave feedback circuit” connected to an output of element 1043.
e) regarding claim 12:
The claim is rejected based on their dependence from claim 11.
f) regarding claim 13:
The limitation, “wherein the leakage-free dummy cell is implemented using an N-type transistor, and a gate of the N-type transistor is connected to an output terminal of the slave data circuit,” fails to comply with the written description. There is no description in the specification of “the master latch comprises a leakage free dummy cell” as recited in claim 1 and that same leakage free dummy cell being “connected to an output terminal of the slave data circuit” as recited in claim 13.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a) regarding claim 15:
It is unclear and therefore indefinite if “a leakage free dummy cell” in lines 1-2 is the same or different from “a leakage free dummy cell” in line 11 of claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,074,603 (hereinafter ‘603 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are a broader recitation of the '603 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use teachings of claims 1-20 of the '603 patent as general teachings of a D flip-flop as claimed in the present application. The instant claims obviously encompass the claimed invention in the '603 patent and differ only in terminology.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,395,159 (hereinafter ‘159 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are a broader recitation of the '159 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use teachings of claims 1-20 of the '159 patent as general teachings of a D flip-flop as claimed in the present application. The instant claims obviously encompass the claimed invention in the '159 patent and differ only in terminology.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rasouli et al. (US 2021/0099161) discloses a master-slave flip flop circuit. Mao (US 2019/0372563) discloses a low power flip-flop circuit.
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/PATRICK O NEILL/ Primary Examiner, Art Unit 2836
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