I. Status of the Application
This action is responsive to the amendment and remarks filed 20 July 2026.
Claims 2, 7 and 11-18 are canceled.
Claims 1, 3-6, 8-10 and 19-21 are pending.
Newly submitted claim 21 is withdrawn from consideration as being directed to a nonelected invention (see Section II).
Claims 1, 3-6, 8-10 and 19-20 are examined herein.
The rejection of claims 1-10 under 35 U.S.C. 112(b) set forth in the Office action of
22 April 2026 is withdrawn in view of the amendment.
The rejection of claims 1 and 3-8 under 35 U.S.C. 102(a)(2) over Jang (US 2023/0005429 A1) is withdrawn in view of the amendment; Jang remains of record as pertinent art.
New grounds of rejection, necessitated by the amendment, are set forth below. THIS ACTION IS MADE FINAL. See Section VI.
II. Election/Restrictions - Withdrawal of Claim 21
Newly submitted claim 21 is directed to an invention that is independent or distinct from elected Invention I (originally claimed on 17 June 2025, restricted on 5 February 2026, elected on 26 March 2026, and examined on 22 April 2026) for the following reasons:
I. Claims 1-10 (as originally submitted on 17 June 2025, restricted on 5 February 2026, and elected on 26 March 2026), drawn to a display device, classified in class G09G 3/3275.
IV. Claim 21 (as newly filed on 20 July 2026), drawn to an electronic device, classified in class G09G 2330/021.
The inventions are distinct, each from the other because of the following reasons:
“Invention I” and “Invention IV” are related respectively as combination and subcombination.
Inventions in this relationship are distinct if it can be shown that: (1) the combination as claimed does not require the particulars of the subcombination as claimed for patentability, and (2) that the subcombination has utility by itself or in other combinations (MPEP § 806.05(c)).
(1) In the instant case, the Combination does not require the particulars of the Subcombination as newly claimed because:
The Combination as claimed (in originally submitted/restricted/elected/examined claims 1-10) does not require:
“the power supply is configured to: supply the first driving power without supplying the second driving power to the data driving circuit in a first mode,” as claimed in newly submitted independent claim 21; and
“the scan driver is configured to generate a first reference power and a second reference power based on the first driving power in the first mode, and generate the first reference power and the second reference power based on the first driving power and the second driving power in the second mode,” as claimed in newly submitted independent claim 21 of “Invention IV.”
Newly submitted claim 21 is drawn to a subcombination of driving circuitry and power supply: it omits the positively recited display panel and its pluralities of data lines and scan lines, reciting the panel only as the object of the power supply’s output (“supply a power voltage to a display panel through power lines”).
(2) Furthermore, the Subcombination has separate utility, such as:
The Subcombination as claimed (in newly submitted claim 21) can be used without requiring:
“a display panel including a plurality of data lines, [and] a plurality of scan lines,” as claimed in originally submitted/restricted/elected/examined independent claim 1 of “Invention I.”
The combination and subcombination are distinct because
(1) the combination as originally claimed and elected did not require the particulars of the subcombination as claimed for patentability - originally presented claim 1 contained neither the “without supplying the second driving power” limitation nor the first/second reference-power limitations now recited in claim 21 - and
(2) the subcombination has utility by itself or in other combinations, in display devices employing panel architectures other than that recited in claim 1, the driving-circuit/power-supply chipset being a separately usable and separately marketable article. See MPEP § 806.05(c).
It is additionally noted that claim 21’s “electronic device” subject matter more closely aligns with withdrawn Invention III and its separate classification; this is corroborative of, and not necessary to, the distinctness showing above.
Restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because at least the following reason(s) apply: The inventions require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries). For example:
Examining of “Invention I” requires employing uniquely different search queries for “a display panel including a plurality of data lines, [and] a plurality of scan lines,” as claimed in originally submitted/restricted/elected independent claim 1 of “Invention I.”
The above search queries would not be required when examining “Invention IV.”
Examining of “Invention IV” requires employing uniquely different search queries for “the power supply is configured to: supply the first driving power without supplying the second driving power to the data driving circuit in a first mode,” as claimed in newly submitted independent claim 21; and
“the scan driver is configured to generate a first reference power and a second reference power based on the first driving power in the first mode, and generate the first reference power and the second reference power based on the first driving power and the second driving power in the second mode,” as claimed in newly submitted independent claim 21 of “Invention IV.”
The above search queries would not be required when examining “Invention I,” as originally presented.
Accordingly, claim 21 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
For clarity of the record: the election of 26 March 2026 fixed the examined subject matter as Invention I; the field of search of record was directed to Invention I, and nothing in the search record converts the claim-21 subcombination into examined subject matter.
It is further noted that the reply of 20 July 2026 did not identify how the added claims are readable on the elected invention, notwithstanding the express requirement of the restriction requirement of record that any claims subsequently added be so identified.
III. Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-6, 8-10 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 1, the final wherein clause recites “generate the first reference power and the second reference power based the first driving power and the second driving power in the second mode” (emphasis added).
The omission of a preposition leaves the basis relation of the clause genuinely uncertain: the clause is amenable to at least two plausible constructions of different scope –
(i) the reference powers are generated based on the first and second driving powers (the reading consistent with the first-mode limb, which recites “based on the first driving power”), or
(ii) a reading in which the recited driving powers stand in apposition to, or as objects of, the generating step, such that the basis relation runs otherwise than in construction (i).
Because the claim, read in light of the specification, is amenable to two or more plausible claim constructions, a rejection under 35 U.S.C. 112(b) is appropriate. See In re Packard, 751 F.3d 1307, 1310, 1314 (Fed. Cir. 2014); MPEP § 2173.02.
Claims 3-6, 8-10 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as depending from claim 1 and thereby incorporating the indefinite limitation identified above.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
A. Claims 1, 8, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 2014/0160182 A1, “Hong”) in view of Han et al. (US 2021/0375209 A1, “Han”).
Regarding claim 1, Hong discloses a display device, comprising:
a display panel including a plurality of data lines, a plurality of scan lines, and a plurality of power lines [e.g., Fig. 1: display panel 300; data lines D1-Dm; gate lines G1-Gn; common-voltage wiring into panel 300; Paragraph 17: “A DC-DC unit applying a common voltage to the display panel” - the panel’s common-voltage/power wiring constituting the power lines];
a data driving circuit including a data driver configured to output a data signal and a scan driver configured to output a scan signal [e.g., Fig. 1: data driver 500; gate driver 400; Paragraph 101: the gray voltage generator 800 “generates voltages required by the data driver circuit 500”; Paragraph 110: “output from the gate driver 400” - the data driver 500 together with the gate driver 400 (a scan driver) constituting the recited data driving circuit under the broadest reasonable interpretation]; and
a power supply configured to supply a power voltage to the display panel through the power lines [e.g., Fig. 1: external power source 700, PMIC unit 650, DC-DC unit 660; Vcom into panel 300; Paragraph 17], and
to selectively supply a first driving power (AVDD) and a second driving power (DVDD) different from the first driving power to the data driving circuit [e.g., Fig. 1: AVDD and DVDD each supplied to data driver 500 and to gray voltage generator 800; PMIC output routes ⑤ (AVDD) and ⑥ (DVDD); Paragraph 115: “the AVDD level is greater than the external power source voltage and is greater than the DVDD level” - the two driving powers differing from one another; published claim 18: the gray voltage generator “configured to receive the digital circuits powering voltage and the analog circuits powering voltage during normal operations”],
wherein the power supply is configured to:
supply the first driving power without supplying the second driving power to the data driving circuit in a first mode [e.g., Paragraph 125: during the new-image blanking time, the input route ③ is blocked such that “a sub-threshold DVDD voltage” results in place of the normal DVDD; Paragraph 126: “at least one of the normal AVDD voltage and the normal DVDD voltage is not” generated; Paragraph 127: output routes selectively blocked such that “the normal AVDD voltage and/or the normal DVDD voltage are not output”; published claim 18: the gray voltage generator “does not receive the digital circuits powering voltage or the analog circuits powering voltage during the new-image blanking time”; Paragraph 21: “the DC-DC unit may continue to receive the analog power source voltage during the blank time” - i.e., a disclosed operating state in which the normal DVDD is withheld while AVDD continues to be supplied]; and
supply both the first driving power and the second driving power to the data driving circuit in a second mode different from the first mode [e.g., published claim 18: receipt of both powering voltages “during normal operations”; Fig. 1; Paragraph 123: the levels “that should be normally generated” - the normal moving-picture display operation constituting the second mode, different from the new-image blanking first mode],
.
Hong further discloses that the gate driver’s output signals “use reference voltages (Von. Voff)” generated from the supplied first driving power [e.g., Paragraph 110; Paragraph 120: the DC-DC unit 660 “uses the received level of the AVDD voltage to correspondingly generate the gate-on voltage Von, the gate-off voltage Voff”], and even contemplates that one of the reference voltages “is generated inside the gate” driver [e.g., Paragraph 110].
Hong does not, however, expressly disclose the struck subject matter above - i.e., a scan driver configured with generation circuitry producing first and second reference powers from the first driving power in the first mode and from both the first and second driving powers in the second mode.
Han teaches a display device in which a voltage generator associated with the scan driver produces the scan driver’s reference powers from a first driving voltage and a second driving voltage:
the voltage generator 180 provides the high voltage VGH, the low voltage VGL, and the negative voltage NVG to the scan driver 200 [e.g., Paragraphs 37, 42; Fig. 9];
the main booster 181 (a first pump) generates VGH “based on the first driving voltage AVDD” [e.g., Paragraph 75; Fig. 9];
the charge pump 190 (a second pump) generates the negative voltage NVG from the first driving voltage AVDD and the second driving voltage NAVDD [e.g., Paragraph 76; Figs. 9-12], its output “corresponding to a sum of the first driving voltage AVDD and an absolute value |NAVDD| of the second driving voltage NAVDD” [e.g., Paragraphs 84, 87; Fig. 12: NVG = -(AVDD + |NAVDD|)] and
the sub booster 183 derives the scan-low rail VGL “based on the negative voltage NVG that the charge pump 190 generates” [e.g., Paragraph 77],
the scan signals being “enabled with a low level” using that rail [e.g., Paragraph 134].
Hong and Han are analogous art, because both are from the same field of endeavor of display devices and their driving and power-supply circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Han’s two-input reference-power generation (main booster and charge pump) as the reference-voltage generation of Hong’s device - i.e., as the generation circuitry of Hong’s gate-driver side, which Hong itself teaches may reside “inside the gate” driver [e.g., Hong Paragraph 110] and which Hong teaches operates from the supplied AVDD [e.g., Hong Paragraph 120] - so that the scan driver’s reference powers are produced from the available AVDD/DVDD pair.
In the combined device, when the normal DVDD is withheld during Hong’s first (new-image blanking) mode, the reference powers are generated from the first driving power alone, and when both driving powers are supplied during normal operation, the reference powers are generated from both, in the manner Han teaches [e.g., Han Paragraphs 75-77, 84, 87].
The motivation is supplied by the references’ own teachings:
Hong’s selective withholding of the normal powering voltages exists so that power is not consumed where not needed, “thereby reducing the overall power consumption of the device” [e.g., Hong Paragraph 161], and
Han’s generator exists to produce the required gate-level voltages, including a sufficiently negative level, from the available driving voltages [e.g., Han Paragraphs 75-76, 87].
The combination unites known prior-art elements according to known methods, each performing its established function, with predictable results. KSR, 550 U.S. at 415-21 (e.g., see Hong Paragraphs 100-127, 139-140 and 161; Han Paragraphs 37-45 and 74- 87).
Regarding claim 8, Hong discloses wherein an absolute value of the second driving power is less than an absolute value of the first driving power [e.g., Paragraph 115: “the AVDD level is greater than the external power source voltage and is greater than the DVDD level”].
Regarding claim 19, Hong in view of Han renders obvious wherein the scan driver comprises:
a first pump configured to output the first reference power for generating a high level signal of the scan signal [e.g., Han Paragraph 75: the main booster 181 generating VGH from the first driving voltage; Han Paragraph 37: VGH received by the scan driver 200; Han Fig. 9 - a booster circuit that pumps the supplied voltage to the higher gate level being a “pump” as claimed under the broadest reasonable interpretation, the claim reciting “pump” without further qualification]; and
a second pump configured to output the second reference power for generating a low level signal of the scan signal [e.g., Han Paragraph 76: the charge pump 190 generating the negative voltage NVG; Han Paragraph 77: the scan-low rail VGL derived “based on the negative voltage NVG”; Han Paragraph 134: the scan signals “enabled with a low level”; Han Figs. 9-12].
The reasons for combining Hong and Han set forth for claim 1 apply.
Regarding claim 20, Hong in view of Han renders obvious wherein the first pump and the second pump are configured to generate the first reference power and the second reference power based on the sum of the first driving power and the second driving power in the second mode [e.g., Han Paragraph 84: the pump capacitor “charged with a voltage corresponding to a sum of the first driving voltage AVDD and an absolute value | NAVDD | of the second driving voltage NAVDD”; Han Paragraph 87; Han Fig. 12].
Han expressly teaches the second pump’s output referenced to the sum of the two driving voltages; configuring the first pump of the combined device likewise on the summed input in the second mode is no more than the predictable selection of a pump input configuration from the finite, known arithmetic options for pump stages operating from the available rails, each yielding a predictable output level. KSR, 550 U.S. at 416-21.
B. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Han as applied to claim 1 above, and further in view of Sakamoto (US 2010/0039354 A1, “Sakamoto”).
Regarding claim 3, Hong in view of Han renders obvious wherein the scan driver includes: a first pump configured to output the first reference power; and a second pump configured to output the second reference power [e.g., Han Paragraphs 75-77; Han Fig. 9; see the treatment of claim 19 above] .
Neither Hong nor Han expressly discloses the two reference powers having the same absolute value.
Sakamoto teaches, for the TFTs of a display panel,
that “a positive voltage of about +25 volts is applied to a gate terminal as the gate signal” at the time of ON operation (the selection state), and
that “a negative voltage of about -25 volts is applied to the gate terminal as the gate signal” at the time of OFF operation (the non-selection state) [e.g., Paragraph 54; see also Paragraph 146: the +25 V “pulse voltage (gate signal)” applied via the gate wiring as the selection level; Paragraph 55: the -25 V level on the gate wiring during the OFF state]
- i.e., gate-on and gate-off levels of equal absolute value (25 V), established as the two operating levels of the scan waveform.
Hong, Han and Sakamoto are analogous art, because all are from the same field of endeavor of display devices employing thin-film-transistor pixel switches driven by gate/scan signals; Sakamoto is additionally reasonably pertinent to the particular problem of establishing the gate-on and gate-off levels for reliable TFT switching.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to configure the first and second pumps of the Hong/Han combination - which establish the high and low levels of the scan signal [e.g., Han Paragraphs 37, 75-77, 134] - such that the second reference power has the same absolute value as the first reference power,
since Sakamoto evidences that gate-on and gate-off levels of equal magnitude are a known and used configuration for driving a display TFT’s gate [e.g., Sakamoto Paragraph 54], and
since the relative magnitudes of two such levels present a finite set of predictable options (the second greater than, equal to, or less than the first) from which the equal-magnitude configuration is a predictable selection with a reasonable expectation of success. KSR, 550 U.S. at 421.
The teaching is applied at the level of the equal-magnitude relationship; the particular 25-volt value of Sakamoto’s electrophoretic panel is not imported into the combination.
C. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Han and Sakamoto as applied to claim 3 above, and further in view of Choi et al. (US 2005/0248388 A1, “Choi”).
Regarding claim 4, Hong in view of Han and Sakamoto renders obvious the display device of claim 3, including the second pump’s output referenced to a sum of the first driving power and the second driving power [e.g., Han Paragraphs 84, 87; Han Fig. 12], but does not expressly disclose the first reference power is a sum of twice the first driving power and the second driving power.
Choi teaches a charge pump of a display driver integrated circuit in which the pump node “is boosted to double the external source voltage VCI” and the resulting “boost voltage AVDD output from the output node of the charge pump circuit 39 is supplied as a source voltage to the circuits 31, 33, 35, and 37 in the LCD driver IC” [e.g., Paragraph 32] - i.e., a driver-internal pump stage whose output is twice its supply input.
Hong, Han, Sakamoto and Choi are analogous art, because all are from the same field of endeavor of display devices and the power-generation circuits of their driver integrated circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to configure the first pump of the combination as a doubling stage of the kind Choi teaches [e.g., Choi Paragraph 32] operating from the first driving power, with the second driving power additionally summed into the output in the second mode in the manner Han teaches for pump-stage summation [e.g., Han Paragraphs 84, 87], yielding a first reference power equal to the sum of twice the first driving power and the second driving power.
Pump-stage multiplication factors and input summations present a finite set of known, predictable arithmetic configurations; selecting the claimed 2x-plus-second-power configuration from among them is the predictable use of known pump arithmetic to obtain a correspondingly predictable output level. KSR, 550 U.S. at 416-21.
D. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Han as applied to claim 1 above, and further in view of Heo et al. (US 2017/0098409 A1, “Heo”).
Claim construction. Claims 5 and 6 recite changing the absolute values of the first and second reference powers “over successive frames.”
Under the broadest reasonable interpretation consistent with the specification, “frames” is construed as successive time frames (periods).
The claims recite no display-frame machinery and tie the recited “frames” to no display-timing structure; the limitation was presented by amendment in place of “at predetermined time intervals”; and applicant’s own remarks characterize the amendment as one in which the prior phrase “has been clarified as” the successive-frames language (Remarks of 20 July 2026 at 6), confirming the temporal-interval scope.
This usage is consistent with the art’s own vocabulary, in which display power-management operation is described by reference to the driving and non-driving sections of each time frame (Choi ‘953, US 2020/0320953 A1, of record, Paragraph 49).
Regarding claim 5, Hong in view of Han renders obvious the display device of claim 1, including reference powers whose levels differ between the first mode (generation from the first driving power alone) and the second mode (generation from both driving powers, at the summed level) [e.g., Han Paragraphs 75-76, 84, 87], but does not expressly disclose wherein the power supply is further configured to change absolute values of the first reference power and the second reference power over successive frames.
Heo teaches a display device whose power supply changes the levels of a pair of scan-rail voltages over successive time frames while maintaining their mutual relationship:
the first scan voltage VSS1 and the second scan voltage VSS2 are held at first levels (V1, V2) during a first period T1 and at different levels (V3, V4) during a second period T2 [e.g., Paragraphs 114-121; Paragraph 117: “The ambient temperature during the first period Tl is lower than that during the second period T2”],
the transition between the level pairs being effected as a coordinated, gradual change spanning the boundary between the successive periods with the delta voltage maintained throughout [e.g., Fig. 5: VSS1 and VSS2 ramping together from V1/V2 to V3/V4 across the T1-T2 transition, AV maintained],
in accordance with Heo’s stated object to “control the level of a scan voltage according to temperature and constantly maintain a difference between a high-level scan voltage and a low-level scan voltage” [e.g., Paragraph 10].
Hong, Han and Heo are analogous art, because all are from the same field of endeavor of display devices and the control of their scan-rail voltage levels.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to effect the reference-power level changes of the Hong/Han combination - which occur when the device transitions between its first and second modes and the generated levels correspondingly change [e.g., Han Paragraphs 84, 87] - as a coordinated change of both reference powers’ absolute values over successive time frames in the manner Heo teaches [e.g., Heo Paragraphs 114-121; Fig. 5], in order to maintain the mutual relationship of the two levels throughout the transition rather than shifting them abruptly and disparately, per Heo’s own stated object [e.g., Heo Paragraph 10].
This is consistent with the recognized behavior of display supply rails at supply-state transitions, whose levels move gradually rather than instantaneously (e.g., see Choi ‘953, of record, Paragraphs 92-94; Figs. 6-7).
The combination applies a known level-transition technique to a known level change, with predictable results. KSR, 550 U.S. at 415-17.
Regarding claim 6, Hong in view of Han and Heo renders obvious wherein the absolute values of the first reference power and the second reference power change as the second driving power increases over the successive frames [e.g., Han Paragraphs 84, 87: the generated reference level corresponding to the sum including the second driving voltage, such that as the second driving power rises upon entry into the second mode, the generated reference powers change correspondingly; Heo Paragraphs 114-121 and Fig. 5 for the change effected over the successive frames as set forth for claim 5].
The reasons for combining set forth for claim 5 apply.
E. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Han as applied to claim 1 above, and further in view of Jeong et al. (US 2016/0133174 A1, “Jeong,” of record).
Regarding claim 9, Hong in view of Han does not expressly disclose the data driver includes: a lookup table configured to store a plurality of gamma voltages corresponding to a luminance range of an image output by the display panel; and a gamma voltage generation circuit configured to select one of the gamma voltages and output the selected gamma voltage as the data signal.
Jeong discloses the data driver includes:
a lookup table [e.g., Figs. 4, 5: 310] configured to store a plurality of gamma voltages corresponding to a luminance range of an image output by the display panel (e.g., see Paragraph 48); and
a gamma voltage generation circuit [e.g., Figs. 4, 5: 340, 350] configured to select one of the gamma voltages and output the selected gamma voltage as the data signal (e.g., see Paragraphs 49-57).
Hong, Han and Jeong are analogous art, because all are from the same field of endeavor of display devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine Jeong’s gamma lookup-table arrangement with the display of the Hong/Han combination, so that the image quality of the display panel may be improved, the combination uniting known prior-art elements by known methods, each performing its established function, with predictable results. KSR, 550 U.S. at 415-17.
Regarding claim 10, Jeong discloses the gamma voltage generation circuit includes first to n-th gamma voltage generators [e.g., Figs. 4, 5: 320, 330] corresponding to n (where n is an integer greater than or equal to 1) luminance ranges, respectively (e.g., see Paragraphs 46-57). The reasons for combining set forth for claim 9 apply.
V. Response to Arguments
Applicant’s arguments filed 20 July 2026 with respect to the rejection of claims 1 and 3-8 under 35 U.S.C. 102(a)(2) over Jang have been fully considered.
That rejection is withdrawn in view of the amendment; the arguments are therefore moot as being directed to a withdrawn ground of rejection, and no reference argued therein is applied against claim 1 in this action.
The amendment’s newly presented limitations - including the selective-supply limitations and the reference-power generation limitations incorporated from canceled claim 2 - necessitated the new grounds of rejection set forth above.
The rejection of claims 1-10 under 35 U.S.C. 112(b) of record is withdrawn in view of the amendment; the rejection under 35 U.S.C. 112(b) set forth in Section III arises from the text as amended.
VI. Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
13 August 2026
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