DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 06/17/25 has been considered by the examiner.
Specification
3. The disclosure is objected to because of the following informalities: on page 1 of the instant specification, reference to parent case 18/350,146 should be updated so as to reflect the fact that this application has now issued as U.S. Patent No. 12,381,552.
Appropriate correction is required.
Claim Objections
4. Claims 1, 7, 12, 14 and 19 are objected to because of the following informalities:
On line 11 of claim 1, the word --is-- should be inserted after "device".
On line 6 of claim 7, the word --and-- should be inserted at the end of the line after the comma.
On line 2 of claim 12, the word "includes" should be changed to --include-- (note line 4 of claim 6 which shows the correct grammatical form of "one or more resistive devices include").
On the second line of claim 14, a comma should be inserted after the word "transistors".
On the second line of claim 19, the word "includes" should again be changed to
--include--, for the same reason noted above in the objection to claim 12.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7 and 12-14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As noted in the parent case, the expression "a high ground voltage" is indefinite because neither the specification nor the claims define how high (or low) the ground voltage would need to be so as to be considered a "high ground voltage", i.e., "high ground" on line 8 of claim 7 should simply be deleted in order to overcome this indefiniteness rejection.
On line 4 of claim 12, "coupled into a resistor" is vague and indefinite, i.e., it cannot be determined by the examiner what is meant by a transistor being "coupled into a resistor". It is noted that a first resistor has already been recited on line 3 of this claim, and it is unclear if the resistor recited on line 4 of claim 12 is referring to the same resistor already set forth on line 3 thereof. Moreover, as noted above, it cannot be determined what is meant by a transistor being "coupled into" a resistor. It appears that applicant simply means that the at least one transistor is coupled to the first resistor, but such is not clear to the examiner, thus rendering claim 12 indefinite under 35 USC 112(b).
Claim 13 is indefinite in view of its dependencies on indefinite claim 12.
Claim 14 is indefinite for the same reason noted above with regard to claim 12, i.e., it cannot be determined by the examiner what is meant by each of the plurality of transistors being "coupled into" a resistor.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maher, U.S. Patent No. 7,378,886.
Maher discloses, in figure 3,
a semiconductor device, comprising:
one or more resistive devices (R3) coupled between a power supply node (the power supply node at the top terminal of resistor R3 which receives power supply voltage Vdd B) and a control node (N1), the power supply node being configured to receive an input/output (IO) supply voltage (Vdd B);
a first transistor (Q3) having
a first gate coupled to receive a core voltage (Vdd A),
a first source/drain (the drain terminal of transistor Q3) coupled to the control node, and
a second source/drain (the source terminal of transistor Q3) configured to receive a first ground voltage which is greater than zero and lower than the IO supply voltage and a peak core voltage level of the core voltage (although Maher does not disclose that the ground voltage received at the source terminal of transistor Q3 is greater than zero and lower than the IO supply voltage and a peak core voltage level of the core voltage, this recitation in claim 15 is just an intended use recitation, the reason being that the voltage received at the source terminal of transistor Q3 is not part of the claimed semiconductor device, but rather what the semiconductor device receives and, moreover, the source terminal of transistor Q3 is clearly capable of receiving a voltage greater than zero and lower than the IO supply voltage and a peak core voltage level of the core voltage); and
a hysteresis block (all of the circuitry shown in figure 3 of Maher to the right of control node N1) connected to the control node and to an output node (the output node for outputting output voltage POREN B), the hysteresis block being configured to generate an output voltage (POREN B) at the output node at either a disabling voltage level or an enabling voltage level in response to the core voltage (note that Maher's hysteresis block is inherently configured to generate an output voltage (POREN B) at the output node at either a disabling voltage level or an enabling voltage level in response to the core voltage, note that it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971)).
7. Claims 1-6, 8 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do, U.S. Patent No. 7,852,129.
As to claim 1, Do discloses, in figure 3,
a semiconductor device, comprising:
a hysteresis block (370) configured to generate an output voltage at a disabling voltage level and at an enabling voltage level (note that hysteresis block 370 is inherently configured to generate an output voltage at a disabling voltage level and at an enabling voltage level), wherein an input terminal (the input terminal of hysteresis block 370 coupled directly to the input of inverter block 372) is coupled to a control node (the control node coupled to the drain terminal of transistor NM31);
a core-voltage-gated (CVG) device (the combination of transistors NM31 and NM32) coupled to the control node, wherein the CVG device includes a first transistor (NM32) and a second transistor (NM31) serially coupled between the control node and a ground node (the ground node receiving VSS) which is configured to receive a ground voltage (VSS),
the first transistor having a first gate configured to receive a core voltage (VDD),
the second transistor having a second gate configured to receive a reference voltage (V_DIV1) at a peak core voltage level of the core voltage (although Do does not disclose that reference voltage V_DIV1 is at a peak core voltage level of the core voltage VDD, this recitation in claim 1 is just an intended use recitation, i.e., the reference voltage received at the gate of the second transistor is not a component of the claimed semiconductor device, but rather simply what the semiconductor device receives and, moreover, transistor NM31 is clearly capable of receiving a reference voltage which is at a peak core voltage level of the core voltage), and
the CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at either the disabling voltage level or the enabling voltage level in response to the core voltage (note that the control voltage at the above-noted control node in Do inherently causes the output voltage of hysteresis block 370 to be generated at either the disabling voltage level or the enabling voltage level in response to core voltage VDD); and
one or more resistive devices (R34) coupled between a power supply node (the power supply node at the top terminal of resistor R34 which receives power supply voltage VDD) and the control node.
As to claim 2, note that the power supply voltage VDD received at the top terminal of resistor R34 can be interpreted as being an input/output (IO) supply voltage, using the test of broadest reasonable interpretation, i.e., because the supply voltage VDD is input to circuit 330 as shown in figure 3 of Do.
As to claim 3, all of the functional limitations set forth in this claim will be inherent during the operation of Do's figure 3 circuitry, as noted above it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971).
As to claim 4, note that voltage VSS shown in Do's figure 3 circuitry is ground voltage at 0V.
As to claim 5, although Do does not indicate that ground voltage VSS is above zero, this recitation is again just an intended use recitation, i.e., the ground voltage received at the source terminal of the first transistor is not a component of the claimed semiconductor device, but rather simply what the semiconductor device receives.
As to claim 6, note that transistor NM32 has its source terminal connected directly to the ground node and its drain terminal coupled to the control node, note that the drain terminals of this transistor is connected indirectly to the above-noted control node via the drain-to-source of transistors NM31.
As to claim 8, note that resistor R34 is connected between the above-noted power supply node and the above-noted control node.
As to claim 15, this claim is rejected using the same analysis as set forth above with regard to claims 1-6 and 8, i.e., the claimed one or more resistive devices is resistor R34, the power supply node is at the top terminal of resistor R34, the first transistor is transistor NM32, the core voltage is VDD, the control node is at the drain terminal of transistor NM31, the hysteresis block is hysteresis block 370, the recitation that the source terminal of the first transistor is coupled to a voltage greater than zero but lower than the IO supply and a peak core level of the core voltage is just a statement of intended use, and the functional limitations recited on the last two lines of claim 15 will be inherent during the operation of Do's figure 3 circuitry, as noted above it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971).
8. Claims 15-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al, U.S. Patent No. 7,295,050.
As to claim 15, Shin et al discloses, in figure 5,
a semiconductor device, comprising:
one or more resistive devices (resistor R3 and/or resistor R4) coupled between a power supply node (the power supply node at the top terminal of resistor R4 which receives power supply voltage Vcc) and a control node (the control node at the drain terminal of transistor N1), the power supply node being configured to receive an input/output (IO) supply voltage (IO supply voltage Vcc, note that supply voltage Vcc can be interpreted as being an IO supply voltage using the test of broadest reasonable interpretation, i.e., it is a supply voltage which is input to circuit 162 at the node connecting the top terminal of resistor R4 to the source terminal of transistor P4)
a first transistor (N1) having
a first gate coupled to receive a core voltage (VA),
a first source/drain (the drain terminal of transistor N1) coupled to the control node, and
a second source/drain (the source terminal of transistor N1) configured to receive a first ground voltage which is greater than zero and lower than the IO supply voltage and a peak core voltage level of the core voltage (although Shin et al does not disclose that the ground voltage received at the source terminal of transistor N1 is greater than zero and lower than the IO supply voltage and a peak core voltage level of the core voltage, this recitation in claim 15 is just an intended use recitation, the reason being that the voltage received at the source terminal of transistor N1 is not part of the claimed semiconductor device, but rather what the semiconductor device receives and, moreover, the source terminal of transistor N1 is clearly capable of receiving a voltage greater than zero and lower than the IO supply voltage and a peak core voltage level of the core voltage); and
a hysteresis block (the combination of inverter chain 20 together with transistor P4) connected to the control node and to an output node (the output node for outputting output voltage VCCH), the hysteresis block being configured to generate an output voltage (VCCH) at the output node at either a disabling voltage level or an enabling voltage level in response to the core voltage (note that Shin et al's hysteresis block is inherently configured to generate output voltage VCCH at the output node at either a disabling voltage level or an enabling voltage level in response to the core voltage, as noted above it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971)).
As to claim 16, note that Shin et al's hysteresis block includes the three inverters IV1 through IV3 and a second transistor P4, the inverters are connected in series between the above-noted control node and the above-noted output node, and the second transistor P4 includes a gate coupled to the output node, a first source/drain (its source terminal) coupled to the power supply node, and a second source/drain (its drain terminal) coupled to the control node, i.e., connected thereto through one (R3) of the one or more resistive devices.
As to claim 17, note that there are three inverters within inverter chain 20.
As to claim 19, the plurality of resistive devices are resistors R3 and R4, and the second source/drain (drain terminal) of the second transistor P4 is coupled to a node between resistors R3 and R4.
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al, supra, in view of Majcherczak et al (USP 6,636,089).
Although Shin et al does not disclose that the drain of second transistor P4 shown in figure 5 of this reference is directly coupled to the control node, such would have been obvious to one of ordinary skill in the art because it was old and well-known in the art before the effective filing date of applicant's invention to connect the drain terminal of a feedback PMOS pull-up transistor within a hysteresis block to the control node of a CVG device, one example of this well-known concept being disclosed by Majcherczak et al (USP 6,636,089), note figure 2 of this reference which shows the drain terminal of transistor M6 being connected directly to the control node Nin within CVG device E1, and note further that one of ordinary skill in the art would have easily recognized that PMOS pull-up transistor P4 shown in figure 5 of Shin et al could alternatively have its drain terminal coupled directly to the control node, i.e., the control node at the drain terminal of transistor N1, of the CVG device 164.
10. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Majcherczak et al, supra.
Majcherczak et al discloses, in figure 2,
a hysteresis block (E3) configured to generate an output voltage (CORE-OFF M) at a disabling voltage level and at an enabling voltage level (the inherent function of hysteresis block E3), wherein an input terminal (the input terminal of hysteresis block E3 coupled directly to the input of inverter IV) of the hysteresis block is coupled to a control node (control node Nin);
a core-voltage-gated (CVG) device (E1) coupled to the control node, wherein the CVG device is configured to receive a core voltage (Vdd) and to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at either the disabling voltage level or the enabling voltage level in response to the core voltage (the inherent function of Majcherczak et al's CVG device); and
one or more resistive devices (any one or more of resistive devices D1, D2 and M1 within block E2) coupled between a power supply node (Vdd3) and the control node,
wherein
the hysteresis block comprises:
a transistor (M6), and
a plurality of inverters connected in series between the control node and an output node configured to output the output voltage (although Majcherczak et al only discloses a single inverter IV coupled between the control node Nin and the output voltage CORE-OFF M, it would have been obvious to one of ordinary skill in the art to include three cascaded inverters in place of the single inverter IV because it was old and well-known in the art before the effective filing date of applicant's invention that a hysteresis block can include either a single inverter or three cascaded inverters, one example of using three cascaded inverters being disclosed by Shin et al, supra, note the three cascaded inverters IV1 through IV3 shown in figure 5 of this reference, and note further that the motivation for replacing the hysteresis block shown in figure 2 of Majcherczak et al with the hysteresis block shown in figure 5 of Shin et al is a simple substitution of one known hysteresis block for another art recognized equivalent hysteresis block, see example (B) discussed in section I of MPEP 2143 which indicates that substitution of one known element for another in order to obtain predictable results would have been obvious to one of ordinary skill in the art), and
the transistor comprises:
a gate (the gate terminal of transistors M6) coupled to the output node,
a first source/drain (the source terminal of transistor M6) coupled to the power supply node, and
a second source/drain (the drain terminal of transistor M6) coupled to the control node.
Double Patenting
11. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,381,552. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations of claims 1-20 are fully anticipated by what is recited in claims 1-20 of applicant's prior patent. Specifically, note that the limitations recited on lines 1-4 of claim 1 of the present application are fully anticipated by what is recited on lines 1-5 of claim 1 of the '552 patent; the limitations recited on lines 5-7 of claim 1 of the present application are fully anticipated by what is recited on lines 6-11 of claim 1 of the '552 patent; the limitations recited on lines 8-10 of claim 1 of the present application are fully anticipated by what is recited on lines 12-15 of claim 1 of the '552 patent; and the limitations recited on lines 11-13 of claim 1 of the present application are fully anticipated by what is recited on lines 15-20 of claim 1 of the '552 patent; and the limitation recited on the last line of claim 1 of the present application is fully anticipated by what is recited on lines 21-25 of claim 1 of the '552 patent. As to claim 2 of the present application, note that the limitation of this claim is fully anticipated by what is recited in claim 2 of the '552 patent. As to claim 3 of the present application, note that the limitation of this claim is fully anticipated by what is recited in claim 3 of the '552 patent. As to claims 4 and 5 of the present application, note that the limitations of these claims are fully anticipated by what is recited in claims 4 and 5, respectively, of the '552 patent. As to claims 6 and 7 of the present application, note that the limitations of these claims are fully anticipated by what is recited in claims 6 and 7, respectively, of the '552 patent. As to claim 8 of the present application, note that the limitation of this claim is fully anticipated by what is recited in claim 9 of the '552 patent. As to claims 9-12 of the present application, note that the limitations of these four claims are fully anticipated by what is recited in claims 8 and 10-12 of the '552 patent. Also note that the limitations of claims 15-20 of the present application are fully anticipated by what is recited in claims 13-20 of the '552 patent.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Allowable Subject Matter
12. Claims 7 and 9-14 would be allowable upon the filing of the above-noted terminal disclaimer.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record discloses or suggests the semiconductor device of claim 6 with the further limitations of a third transistor having a semiconductor type opposite from a semiconductor type of the first transistor and the second transistor, wherein the second transistor further includes a first source/drain coupled to a second source/drain of the first transistor, and a second source/drain, and the third transistor includes a third gate configured to receive a voltage above ground voltage, a first source/drain coupled to the control node, and a second source/drain coupled to the second source/drain of the second transistor, as recited in claim 7; nor does any of the prior art of record disclose or suggest the semiconductor device of claim 1 with the further limitations that the hysteresis block includes inverters and a third transistor, the third inverters being connected in series between the control node and the output node, the third transistor including a third gate coupled to the output node, a first source/drain coupled to the power supply node, and a second source/drain coupled to the control node, either directly or through one or more of the resistive devices, as recited in claim 9. Claims 10-14 are allowable in view of their dependencies, directly or indirectly, on allowable claim 9.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 August 21, 2026
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