DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a) regarding claim 4:
Claim 4 recites the limitations "the first FF" and “the second FF” in lines 1 and 2, respectively. There is insufficient antecedent basis for these limitations in the claim.
b) regarding claims 5-7:
The claims are rejected based on their dependence from claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, 12, 13, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US Patent No. 9,291,674).
a) regarding claim 1:
Lu et al. discloses a shift register (Figure 4A), comprising:
a sequential logic circuit (402 and 404), configured to receive an input data;
a gating circuit (416), configured to disable a portion of the sequential logic circuit for storing a portion of the input data according to data currently being stored in the sequential logic circuit during a writing cycle for writing the entire input data to the shift register (column 9, line 48-column 10, line 23).
b) regarding claim 2:
Lu et al. discloses the shift register of claim 1, wherein the sequential logic circuit comprises:
a first flip-flop (FF) (402), configured to receive a first portion of the input data;
a second FF (404), coupled to the first FF in series and configured to receive a second portion of the input data subsequent to the first portion of the input data.
c) regarding claim 3:
Lu et al. discloses the shift register of claim 2, wherein the gating circuit (416) is configured to disable for the second FF (404) for storing the second portion of the entire input data according to the output data of the first FF (column 9, lines 48-65).
d) regarding claim 9:
Lu et al. discloses the shift register of claim 1, further comprising:
a clock gating circuit (428), including a first input terminal coupled to a clock signal (Clock signal), a second input terminal coupled to the gating circuit (422-426), and an output terminal (VCLK_INT) coupled to a clock terminal of a second portion (404) of the sequential logic circuit coupled to a first portion (402) of the sequential logic circuit in series, and configured to gate the clock signal from the second portion of the sequential logic circuit based on a gating enable signal (VCS2) output by the gating circuit (column 8, lines 9-13).
e) regarding claim 12:
Lu et al. discloses a shift register (Figure 5), comprising:
a first logic circuit (502 and 504), receiving and storing a first portion of an input data;
a second logic circuit (506), receiving and storing a second portion of the input data;
a gating circuit (510), disabling the second logic circuit for storing the second portion of the entire input data according to a current logic at an output terminal of the first logic circuit while storing the first portion of the subsequent input data to the first logic circuit during at least one writing cycle of the shift register (column 11, lines 1-15).
f) regarding claim 13:
Lu et al. discloses the shift register of claim 12, wherein the first logic circuit (502 and 504) comprises:
a first flip-flop (FF) (502) and a third FF (504) coupled between the first FF (502) and the second logic circuit (506), configured to store the first portion of the input data, wherein the third FF (504) is configured to receive a third portion of the input data, and the third portion of the input data is between the first and second portions of the input data (column 10, lines 28-46 and 58-67).
g) regarding claim 19:
Lu et al. discloses the shift register of claim 12, further comprising:
a clock gating circuit (522), including a first input terminal coupled to a clock signal (Clock signal), a second input terminal coupled to the gating circuit 516-520), and an output terminal (VCLK_INT2) coupled to a clock terminal of the second logic circuit (506), and configured to gate the clock signal from the second logic circuit based on a gating enable signal (VCS2) output by the gating circuit (column 11, lines 6-9).
h) regarding claim 20:
Lu et al. discloses a method for disabling flip-flop(s) (FF) in a shift register (Figure 4A) which is configured to handle an input data including a first bit and a second bit, comprising:
loading current data stored in a first FF (402); and
disabling a second FF (404) subsequent to the first FF for storing the second bit of the input data according to the current data stored in the first FF while writing the first bit of the input data to the first FF during at least one entire data writing cycle of the shift register (column 9, line 48-column 10, line 23).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,990,194 (hereinafter ‘194 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are a broader recitation of the '194 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use the teachings of claims 1-20 of the '194 patent as general teachings of an information generation device as claimed in the present application. The instant claims obviously encompass the claimed invention in the '194 patent and differ only in terminology.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,362,027 (hereinafter ‘027 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are a broader recitation of the '194 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use the teachings of claims 1-20 of the '027 patent as general teachings of an information generation device as claimed in the present application. The instant claims obviously encompass the claimed invention in the '027 patent and differ only in terminology.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Parnami et al. (US 9,312,834) discloses a low leakage flip-flop circuit using a clock gating cell. Moon (US 2010/0214854) discloses a shift register capable of glitch-free operation when transitioning between power-saving and active modes of operation. Tso et al. (US 2008/0260090) discloses a shift register with power saving capability.
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/PATRICK O NEILL/ Primary Examiner, Art Unit 2836
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