DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
2. A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
3. Claims 1-7 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-7 of U.S. Patent 12,362,330 B2.
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claim 15 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,362,330. Although the conflicting claims are not identical, they are not patentably distinct from each other because said claim of the above-identified U.S. Patent contains all elements of said claim of the present invention.
Specifically, the conflicting claims are listed below:
Application Claim
Patent Claim
Patent claim 5:
(The device according to claim 1)
15. A 3D semiconductor device, the device comprising:
[[1.]] A 3D semiconductor device, the device comprising:
a first level,
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
a second level overlaying said first level,
wherein said second level comprises a plurality of second transistors,
wherein said second level comprises a plurality of second transistors,
wherein said second level comprises a third layer, said third layer comprising first conductive lines;
wherein said second level comprises a third layer, said third layer comprising first conductive lines;
a third level overlaying said second level,
a third level overlaying said second level,
wherein said third level comprises a plurality of third transistors,
wherein said third level comprises a plurality of third transistors,
wherein said third level comprises a fourth layer, said fourth layer comprising second conductive lines; and
wherein said third level comprises a fourth layer, said fourth layer comprising second conductive lines; and
a plurality of connection paths,
a plurality of connection paths,
wherein said plurality of connection paths provides electrical connections from a plurality of said first transistors to said plurality of third transistors,
wherein said plurality of connection paths provides electrical connections at least from a plurality of said first transistors to said plurality of third transistors, and
wherein said first level comprises at least one voltage regulator[[.]]
wherein said first level comprises a first data bus,
wherein said first level comprises a first data bus, (and)
wherein said third level comprises a second data bus, and
wherein said third level comprises a second data bus, and
wherein at least one of said connection paths comprises an electrical connection between said first data bus and said second data bus.
wherein at least one of said connection paths comprises an electrical connection between said first data bus and said second data bus.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 15 and 18 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference).
The reference discloses in Figs. 1-4 and 17 and related text a 3D semiconductor device as claimed.
Referring to claim 15, the ‘776 reference discloses a 3D semiconductor device, the device comprising:
a first level (10A, Fig. 17),
wherein said first level comprises a first layer (100, Figs. 3, 17), said first layer (100) comprising first transistors (MT and/or ST, Fig. 2; specifically, para [46] (paragraph(s) [0046]): “memory array area 100 embraces the memory cell array 11”, para [36]: “FIG. 2 is a circuit diagram of the block BLK included in the memory cell array 11”, para [37]: “NAND strings NS each include, for example, eight memory cell transistors MT0 to MT7, and select transistors ST1 and ST2”), and
wherein said first level (10A) comprises a second layer (lower 200, Figs. 3, 17), said second layer (200) comprising first interconnections (such as right via 31 and right contact plug CP5B, para [47, 59] (paragraph(s) [0047], [0059]));
a second level (10B, Fig. 17) overlaying said first level (10A),
wherein said second level comprises a plurality of second transistors (MT and/or ST of 100 of 10B),
wherein said second level (10B) comprises a third layer (middle 200, Fig. 17), said third layer comprising first conductive lines (right conductive layers 35, para [59], of the middle 200);
a third level (10C, Fig. 17) overlaying said second level (10B),
wherein said third level (10C) comprises a plurality of third transistors (MT and/or ST of 100 of 10C),
wherein said third level (10C) comprises a fourth layer (upper 200, Fig. 17), said fourth layer comprising second conductive lines (right conductive layers 35 of the upper 200); and
a plurality of connection paths (contact plugs/pads/vias CP3/47/31/CP5B/CP6, para [53, 47, 59-60),
wherein said plurality of connection paths (CP3/47/31/CP5B/CP6) provides electrical connections from a plurality of said first transistors (MT and/or ST of 100 of 10A) to said plurality of third transistors (MT and/or ST of 100 of 10C) (and note that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]),
wherein said first level (10A) comprises a first data bus (wordline/bitline WL/BL (para [38, 39]) of memory array 100 of level 10A),
wherein said third level (10C) comprises a second data bus (wordline/bitline WL/BL of memory array 100 of level 10C), and
wherein at least one (such as driver 13, address register 15 and command register 16, Fig. 1, para [22, 24) of said connection paths (CP3/47/31/CP5B/CP6) comprises an electrical connection between said first data bus and said second data bus (note again that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]) (see also paragraph(s) [0113]-[0116]).
Referring to claim 18, the reference further discloses that
said second level (10B) is bonded to said first level (10A),
said bonded comprises oxide-to-oxide bond regions (those of insulation 48 (para [54]) and insulation silicon oxide 36, para [60]),
and that said bonded additionally comprises metal-to-metal bond regions (those of pads 37 and 49, formed of metal copper or metal aluminum, para [54, 60]) made on a same level as said oxide-to-oxide bonds.
7. Claims 1, 4-5, 7, 15, 17-18 and 20 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference).
The reference discloses in Fig. 16 and other figures and related text a 3D semiconductor device as claimed.
Referring to claim 1, the ‘753 reference discloses a 3D semiconductor device, the device comprising:
a first level (1696, including peripheral circuit, para [303]),
wherein said first level comprises a first layer (1667/1606), said first layer (1667/1606) comprising first transistors (para [317]), and
wherein said first level (1696) comprises a second layer (1668), said second layer (1668) comprising first interconnections (1668, para [318);
a second level (1694) overlaying said first level (1696),
wherein said second level comprises a plurality of second transistors (para [314]: DFM cells 1644 (of second level 1694, see Fig. 16)), wherein the DFM cells include transistors, para [84]
wherein said second level (1694) comprises a third layer (1648), said third layer comprising first conductive lines (at the bottom of 1648, electrically connecting to cells 1644, contact 1649 (para [316]), and pads of interconnections 1668);
a third level (1692) overlaying said second level (1694),
wherein said third level (1692) comprises a plurality of third transistors (para [306]: NAND string 1624 (of third level 1692, see Fig. 16), wherein the NAND string includes transistors, para [138], see also Fig. 2),
wherein said third level (1692) comprises a fourth layer (interconnection layer 1628, para [310]), said fourth layer comprising second conductive lines (at the top of 1628, electrically connecting to NAND string 1624, contact 1629 (para [311]), and pads of interconnections 1688, para [324); and
a plurality of connection paths (through contacts 1669/1649/1629, para [320, 316, 311]),
wherein said plurality of connection paths (1669/1649/1629) provides electrical connections at least from a plurality of said first transistors (of said first layer 1667/1606) to said plurality of third transistors (of said NAND string 1624), and
wherein said first level (1696) comprises at least one voltage regulator (851, para [179], by generator 810 of the peripheral circuit, para [178] included in the first level 1696, para [303]).
Referring to claim 15 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a 3D semiconductor device, the device comprising:
a first level (1696),
wherein said first level comprises a first layer (1667/1606), said first layer comprising first transistors (para [317]), and
wherein said first level (1696) comprises a second layer (1668), said second layer comprising first interconnections (1668);
a second level (1694) overlaying said first level (1696),
wherein said second level comprises a plurality of second transistors (DFM cells 1664),
wherein said second level (1694) comprises a third layer (1648), said third layer comprising first conductive lines (at the bottom of 1648);
a third level (1692) overlaying said second level (1694),
wherein said third level (1692) comprises a plurality of third transistors (of NAND string 1624),
wherein said third level (1692) comprises a fourth layer (1628), said fourth layer comprising second conductive lines (at the top of 1628); and
a plurality of connection paths (through contacts 1669/1649/1629),
wherein said plurality of connection paths (through contacts 1669/1649/1629) provides electrical connections from a plurality of said first transistors (of said first layer 1667/1606) to said plurality of third transistors (of said NAND string 1624),
wherein said first level (1696, that includes peripheral circuit) comprises a first data bus (that electrically connect to wordline/bitline of the NAND string, para [113, 115]]),
wherein said third level (1692) comprises a second data bus (wordline/bitline of the NAND string 1624), and
wherein at least one of said connection paths (through contacts 1669/1649/1629) comprises an electrical connection between said first data bus and said second data bus.
Referring to claims 4 and 18, the reference further discloses that said second level (1694) is bonded to said first level (1696), wherein said bonded comprises oxide-to-oxide bond regions (the dielectric layers (not labeled, para [203]) of the first level and the second level are notoriously formed of oxide, thus forming oxide-to-oxide bond regions), wherein said bonded additionally comprises metal-to-metal bond regions (the pads, not labeled, of interconnecting layer 1668 and conductive layers, not labeled, of the second level 1694 are formed of metal, para [113]) made on a same level as said oxide-to-oxide bond regions.
Referring to claim 5, the reference further discloses
wherein said first level (1696, that includes peripheral circuit) comprises a first data bus (that electrically connect to wordline/bitline of the NAND string, para [113, 115]]),
wherein said third level (1692) comprises a second data bus (wordline/bitline of the NAND string 1624), and
wherein at least one of said connection paths (through contacts 1669/1649/1629) comprises an electrical connection between said first data bus and said second data bus.
Referring to claims 7 and 20, the reference further discloses that said first level (1696, including peripheral circuit, para [303]) comprises at least one control circuit (row decoder, word line driver, para [126]), wherein said second level (1694) comprises at least one memory array (para [303]), and wherein said at least one control circuit controls data written to said at least one memory array (via bit lines and word lines).
Referring to claim 17, the reference further discloses that said first level (1696) comprises at least one voltage regulator (851, para [179], by generator 810 of the peripheral circuit, para [178] included in the first level 1696, para [303]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 16 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Liu et al. U.S. Patent Application Publication 20110128042.
Referring to claim 16, the ‘776 reference discloses a 3D semiconductor device including the first level as detailed above for claim 15, but does not disclose that said first level comprises at least one PLL circuit. However, the first level of the 3D semiconductor device requires a PLL circuit to operate, albeit external to the first level.
Liu, in disclosing a semiconductor device comprising a level (chip 10, Fig. 4, para [47]), teaches that the level comprises a PLL circuit (phase lock loop circuit, para [61]) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776 reference’s first level comprising at least one PLL circuit. One would have been motivated to make such a modification in view of the teachings in Liu for the implied purpose of monolithically integrating the at least PLL into the level.
9. Claims 2 and 16 are rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Liu et al. U.S. Patent Application Publication 20110128042.
Referring to claim 16, the ‘753 reference discloses a 3D semiconductor device including the first level as detailed above for claims 1 and 15, but does not disclose that said first level comprises at least one PLL circuit. However, the first level of the 3D semiconductor device requires a PLL circuit to operate, albeit external to the first level.
Liu, in disclosing a semiconductor device comprising a level (chip 10, Fig. 4, para [47]), teaches that the level comprises a PLL circuit (phase lock loop circuit, para [61]) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘753 reference’s first level comprising at least one PLL circuit. One would have been motivated to make such a modification in view of the teachings in Liu for the implied purpose of monolithically integrating the at least PLL into the level.
10. Claim 17 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854.
Referring to claim 17, the ‘776 reference discloses a 3D semiconductor device including the first level as detailed above for claim 15, but does not disclose that said first level comprises at least one voltage regulator. However, the first level of the 3D semiconductor device requires a voltage regulator to operate or to operate safely, albeit external to the first level.
Huang, in disclosing a semiconductor device comprising a level (Fig. 1), teaches that the level comprises a voltage regulator (30, col. 3, lines 45-50) for protection of the level (col. 1, lines 5-10); or, Chu, in disclosing a semiconductor device comprising a level (200, Fig. 4), teaches that the level comprises a voltage regulator (441, para [31]) for the implied purpose of monolithically integrating the voltage regulator into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776 reference’s first level comprising at least one voltage regulator. One would have been motivated to make such a modification in view of the teachings in Huang for protection of the level or in view of the teachings of Chu for the implied purpose of monolithically integrating the at least one voltage regulator into the level.
11. Claim 19 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Azeroual U.S. Patent 8,803,339.
Referring to claim 3, the ‘776 reference discloses the first level as detailed above for claim 1, but does not disclose said first level comprises at least one SerDes circuit. However, the first level of the 3D semiconductor device requires a SerDes circuit to operate, albeit external to the first level.
Azeroual, in disclosing a semiconductor device comprising a level (chip 100, Fig. 1A, col. 4, lines 1-8), teaches that the level comprises a SerDes (serializer/deserializer) circuit, col. 4, lines 1-8) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776 reference’s first level comprising at least one SerDes circuit. One would have been motivated to make such a modification in view of the teachings in Azeroual for the implied purpose of monolithically integrating the at least SerDes into the level.
12. Claims 3 and 19 are rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Azeroual U.S. Patent 8,803,339.
Referring to claim 3, the ‘753 reference discloses the first level as detailed above for claim 1, but does not disclose said first level comprises at least one SerDes circuit. However, the first level of the 3D semiconductor device requires a SerDes circuit to operate, albeit external to the first level.
Azeroual, in disclosing a semiconductor device comprising a level (chip 100, Fig. 1A, col. 4, lines 1-8), teaches that the level comprises a SerDes (serializer/deserializer) circuit, col. 4, lines 1-8) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘753 reference’s first level comprising at least one SerDes circuit. One would have been motivated to make such a modification in view of the teachings in Azeroual for the implied purpose of monolithically integrating the at least SerDes into the level.
13. Claim 6 is rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Luo et al. U.S. Patent Application Publication 20130119527.
Referring to claim 6, the ‘753 reference discloses the first level and the second level as detailed above for claim 1, and further discloses that said first level comprises a first die area and said second level comprises a second die area, but does not disclose that said first die area is greater than said second die area.
Luo, in disclosing a 3D semiconductor device comprising a first level (peripheral circuitry (logic) chip 102, Fig. 1, para [20]) having a first die area and a second level (memory chip 108a, para [21]) having a second die area, teaches that said first die area is greater than said second die area to increase power density (para [21]: “…extending area 112 of logic die 102,… comprise a relatively higher power density region 114”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘753 reference’s 3D semiconductor device with said first die area being greater than said second die area. One would have been motivated to make such a modification in view of the teachings in Luo to increase power density.
14. Claims 1 and 4-5 are rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854.
Referring to claim 1, the ‘776 reference discloses a 3D semiconductor device including a first level, but does not disclose that said first level comprises at least one voltage regulator. However, the first level of the 3D semiconductor device requires a voltage regulator to operate or to operate safely, albeit external to the first level.
Huang, in disclosing a semiconductor device comprising a level (Fig. 1), teaches that the level comprises a voltage regulator (30, col. 3, lines 45-50) for protection of the level (col. 1, lines 5-10); or, Chu, in disclosing a semiconductor device comprising a level (200, Fig. 4), teaches that the level comprises a voltage regulator (441, para [31]) for the implied purpose of monolithically integrating the voltage regulator into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776 reference’s first level comprising at least one voltage regulator. One would have been motivated to make such a modification in view of the teachings in Huang for protection of the level or in view of the teachings of Chu for the implied purpose of monolithically integrating the at least one voltage regulator into the level.
Thus, such a modification would have resulted in or wherein:
referring to claim 1, a 3D semiconductor device, the device comprising:
a first level (10A, Fig. 17),
wherein said first level comprises a first layer (100, Figs. 3, 17), said first layer (100) comprising first transistors (MT and/or ST, Fig. 2; specifically, para [46] (paragraph(s) [0046]): “memory array area 100 embraces the memory cell array 11”, para [36]: “FIG. 2 is a circuit diagram of the block BLK included in the memory cell array 11”, para [37]: “NAND strings NS each include, for example, eight memory cell transistors MT0 to MT7, and select transistors ST1 and ST2”), and
wherein said first level (10A) comprises a second layer (lower 200, Figs. 3, 17), said second layer (200) comprising first interconnections (such as right via 31 and right contact plug CP5B, para [47, 59] (paragraph(s) [0047], [0059]));
a second level (10B, Fig. 17) overlaying said first level (10A),
wherein said second level comprises a plurality of second transistors (MT and/or ST of 100 of 10B),
wherein said second level (10B) comprises a third layer (middle 200, Fig. 17), said third layer comprising first conductive lines (right conductive layers 35, para [59], of the middle 200);
a third level (10C, Fig. 17) overlaying said second level (10B),
wherein said third level (10C) comprises a plurality of third transistors (MT and/or ST of 100 of 10C),
wherein said third level (10C) comprises a fourth layer (upper 200, Fig. 17), said fourth layer comprising second conductive lines (right conductive layers 35 of the upper 200); and
a plurality of connection paths (contact plugs/pads/vias CP3/47/31/CP5B/CP6, para [53, 47, 59-60),
wherein said plurality of connection paths (CP3/47/31/CP5B/CP6) provides electrical connections at least from a plurality of said first transistors (MT and/or ST of 100 of 10A) to said plurality of third transistors (MT and/or ST of 100 of 10C) (and note that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]), and
wherein said first level (10A) would have comprised at least one voltage regulator (as taught by Sugisaki or Huang);
referring to claim 4.
said second level (10B) is bonded to said first level (10A),
said bonded comprises oxide-to-oxide bond regions (those of insulation 48 (para [54]) and insulation silicon oxide 36, para [60]),
and wherein said bonded additionally comprises metal-to-metal bond regions (those of pads 37 and 49, formed of metal copper or metal aluminum, para [54, 60]) made on a same level as said oxide-to-oxide bonds;
and
referring to claim 5.
said first level comprises a first data bus (wordline/bitline WL/BL (para [38, 39]) of memory array 100 of level 10A),
said third level (10C) comprises a second data bus (wordline/bitline WL/BL of memory array 100 of level 10C), and
at least one (such as driver 13, address register 15 and command register 16, Fig. 1, para [22, 24) of said connection paths (CP3/47/31/CP5B/CP6) comprises an electrical connection between said first data bus and said second data bus (note that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]) (see also paragraph(s) [0113]-[0116]).
14.1. Claim 2 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854 as detailed above for claim 1 and further in view of Liu et al. U.S. Patent Application Publication 20110128042.
Referring to claim 2, the ‘776 in view of Huang or Chu (‘776/Huang or ‘776/Chu) discloses the first level as detailed above for claim 1, but does not disclose said first level comprises at least one PLL circuit. However, the first level of the 3D semiconductor device requires a PLL circuit to operate, albeit external to the first level.
Liu, in disclosing a semiconductor device comprising a level (chip 10, Fig. 4, para [47]), teaches that the level comprises a PLL circuit (phase lock loop circuit, para [61]) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776/Huang’s or ‘776/Chu’s first level comprising at least one PLL circuit. One would have been motivated to make such a modification in view of the teachings in Liu for the implied purpose of monolithically integrating the at least PLL into the level.
14.2. Claim 3 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854 as detailed above for claim 1 and further in view of Azeroual U.S. Patent 8,803,339.
Referring to claim 3, the ‘776 in view Huang or Chu (‘776/ Huang or ‘776/Chu) discloses the first level as detailed above for claim 1, but does not disclose said first level comprises at least one SerDes circuit. However, the first level of the 3D semiconductor device requires a SerDes circuit to operate, albeit external to the first level.
Azeroual, in disclosing a semiconductor device comprising a level (chip 100, Fig. 1A, col. 4, lines 1-8), teaches that the level comprises a SerDes (serializer/deserializer) circuit, col. 4, lines 1-8) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776/ Huang’s or ‘776/Chu’s first level comprising at least one SerDes circuit. One would have been motivated to make such a modification in view of the teachings in Azeroual for the implied purpose of monolithically integrating the at least SerDes into the level.
14.3. Claim 6 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854 as detailed above for claim 1 and further in view of in view of Luo et al. U.S. Patent Application Publication 20130119527.
Referring to claim 6, the ‘776 in view Huang or Chu (‘776/ Huang or ‘776/Chu) discloses
the first level and the second level as detailed above for claim 1, and further discloses that said first level comprises a first die area and said second level comprises a second die area, but does not disclose that said first die area is greater than said second die area.
Luo, in disclosing a 3D semiconductor device comprising a first level (peripheral circuitry (logic) chip 102, Fig. 1, para [20]) having a first die area and a second level (memory chip 108a, para [21]) having a second die area, teaches that said first die area is greater than said second die area to increase power density (para [21]: “…extending area 112 of logic die 102,… comprise a relatively higher power density region 114”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776/ Huang’s or ‘776/Chu’s 3D semiconductor device with said first die area being greater than said second die area. One would have been motivated to make such a modification in view of the teachings in Luo to increase power density.
15. Claims 8 and 11-12 are rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945.
Referring to claim 8, the ‘776 reference discloses a 3D semiconductor device including a first level, but does not disclose that said first level comprises at least one temperature sensor.
Kawano, in disclosing a semiconductor device comprising a level (CP, Fig. 14), teaches that the level comprises a temperature sensor for protection of the level (para [109]); or, Sato, in disclosing a semiconductor device comprising a level (301, Fig. 3), teaches that the level comprises a voltage regulator (309) so that internal temperature of the level can be monitored (para [53]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776 reference’s first level comprising at least one temperature sensor. One would have been motivated to make such a modification in view of the teachings in Kawano for protection of the level or in view of the teachings of Sato so that internal temperature of the level can be monitored.
Thus, such a modification would have resulted in or wherein:
referring to claim 8, a 3D semiconductor device, the device comprising:
a first level (10A, Fig. 17),
wherein said first level comprises a first layer (100, Figs. 3, 17), said first layer (100) comprising first transistors (MT and/or ST, Fig. 2; specifically, para [46] (paragraph(s) [0046]): “memory array area 100 embraces the memory cell array 11”, para [36]: “FIG. 2 is a circuit diagram of the block BLK included in the memory cell array 11”, para [37]: “NAND strings NS each include, for example, eight memory cell transistors MT0 to MT7, and select transistors ST1 and ST2”), and
wherein said first level (10A) comprises a second layer (lower 200, Figs. 3, 17), said second layer (200) comprising first interconnections (such as right via 31 and right contact plug CP5B, para [47, 59] (paragraph(s) [0047], [0059]));
a second level (10B, Fig. 17) overlaying said first level (10A),
wherein said second level comprises a plurality of second transistors (MT and/or ST of 100 of 10B),
wherein said second level (10B) comprises a third layer (middle 200, Fig. 17), said third layer comprising first conductive lines (right conductive layers 35, para [59], of the middle 200);
a third level (10C, Fig. 17) overlaying said second level (10B),
wherein said third level (10C) comprises a plurality of third transistors (MT and/or ST of 100 of 10C),
wherein said third level (10C) comprises a fourth layer (upper 200, Fig. 17), said fourth layer comprising second conductive lines (right conductive layers 35 of the upper 200); and
a plurality of connection paths (contact plugs/pads/vias CP3/47/31/CP5B/CP6, para [53, 47, 59-60),
wherein said plurality of connection paths (CP3/47/31/CP5B/CP6) provides electrical connections from a plurality of said first transistors (MT and/or ST of 100 of 10A) to said plurality of third transistors (MT and/or ST of 100 of 10C) (and note that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]),
wherein said first level (10A) would have comprised at least one temperature sensor (as taught by Kawano or Sato));
referring to claim 11,
wherein said first level (10A) comprises a first data bus (wordline/bitline WL/BL (para [38, 39]) of memory array 100 of level 10A),
wherein said third level (10C) comprises a second data bus (wordline/bitline WL/BL of memory array 100 of level 10C), and
wherein at least one (such as driver 13, address register 15 and command register 16, Fig. 1, para [22, 24) of said connection paths (CP3/47/31/CP5B/CP6) comprises an electrical connection between said first data bus and said second data bus (note again that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]) (see also paragraph(s) [0113]-[0116]);
referring to claim 12.
said first level comprises a first data bus (wordline/bitline WL/BL (para [38, 39]) of memory array 100 of level 10A),
said third level (10C) comprises a second data bus (wordline/bitline WL/BL of memory array 100 of level 10C), and
at least one (such as driver 13, address register 15 and command register 16, Fig. 1, para [22, 24) of said connection paths (CP3/47/31/CP5B/CP6) comprises an electrical connection between said first data bus and said second data bus (note that peripheral circuits 200 of levels 10A-10C embrace circuits 12-17, para [46]) (see also paragraph(s) [0113]-[0116]).
15.1. Claim 9 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945 and further in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854.
Referring to claim 9, the ‘776 reference in view of Kawano or Sato (‘776/Kawano or ‘776/Sato) discloses a 3D semiconductor device including a first level as detailed above for claim 8, but does not disclose that said first level comprises at least one voltage regulator. However, the first level of the 3D semiconductor device requires a voltage regulator to operate or to operate safely, albeit external to the first level.
Huang, in disclosing a semiconductor device comprising a level (Fig. 1), teaches that the level comprises a voltage regulator (30, col. 3, lines 45-50) for protection of the level (col. 1, lines 5-10); or, Chu, in disclosing a semiconductor device comprising a level (200, Fig. 4), teaches that the level comprises a voltage regulator (441, para [31]) for the implied purpose of monolithically integrating the voltage regulator into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776/Kawano’s or ‘776/Sato’s first level comprising at least one voltage regulator. One would have been motivated to make such a modification in view of the teachings in Huang for protection of the level or in view of the teachings of Chu for the implied purpose of monolithically integrating the at least one voltage regulator into the level.
15.2. Claim 10 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945 as detailed above for claim 8 and further in view of Azeroual U.S. Patent 8,803,339.
Referring to claim 10, the ‘776 reference in view of Kawano or Sato (‘776/Kawano or ‘776/Sato) discloses a 3D semiconductor device including a first level as detailed above for claim 8, but does not disclose said first level comprises at least one SerDes circuit. However, the first level of the 3D semiconductor device requires a SerDes circuit to operate, albeit external to the first level.
Azeroual, in disclosing a semiconductor device comprising a level (chip 100, Fig. 1A, col. 4, lines 1-8), teaches that the level comprises a SerDes (serializer/deserializer) circuit, col. 4, lines 1-8) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776/Kawano’s or ‘776/Sato’s first level comprising at least one SerDes circuit. One would have been motivated to make such a modification in view of the teachings in Azeroual for the implied purpose of monolithically integrating the at least SerDes into the level.
15.3. Claim 13 is rejected under 35 U.S.C. §103 as being unpatentable over Sugisaki U.S. Patent Application Publication 2020/0098776 A1 (the ‘776 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945 as detailed above for claim 8 and further in view of Liu et al. U.S. Patent Application Publication 20110128042.
Referring to claim 13, the ‘776 reference in view of Kawano or Sato (‘776/Kawano or ‘776/Sato) discloses a 3D semiconductor device including a first level as detailed above for claim 8, but does not disclose said first level comprises at least one PLL circuit. However, the first level of the 3D semiconductor device requires a PLL circuit to operate, albeit external to the first level.
Liu, in disclosing a semiconductor device comprising a level (chip 10, Fig. 4, para [47]), teaches that the level comprises a PLL circuit (phase lock loop circuit, para [61]) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776/Kawano’s or ‘776/Sato’s first level comprising at least one PLL circuit. One would have been motivated to make such a modification in view of the teachings in Liu for the implied purpose of monolithically integrating the at least PLL into the level.
16. Claims 8-9, 11-12 and 14 are rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945.
Referring to claim 8, the ‘753 reference discloses a 3D semiconductor device including a first level, but does not disclose that said first level comprises at least one temperature sensor.
Kawano, in disclosing a semiconductor device comprising a level (CP, Fig. 14), teaches that the level comprises a temperature sensor for protection of the level (para [109]); or, Sato, in disclosing a semiconductor device comprising a level (301, Fig. 3), teaches that the level comprises a voltage regulator (309) so that internal temperature of the level can be monitored (para [53]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘776 reference’s first level comprising at least one temperature sensor. One would have been motivated to make such a modification in view of the teachings in Kawano for protection of the level or in view of the teachings of Sato so that internal temperature of the level can be monitored.
Thus, such a modification would have resulted in or wherein:
referring to claim 8, a 3D semiconductor device, the device comprising:
a first level (1696),
wherein said first level comprises a first layer (1667/1606), said first layer comprising first transistors (para [317]), and
wherein said first level (1696) comprises a second layer (1668), said second layer comprising first interconnections (1668);
a second level (1694) overlaying said first level (1696),
wherein said second level comprises a plurality of second transistors (DFM cells 1664),
wherein said second level (1694) comprises a third layer (1648), said third layer comprising first conductive lines (at the bottom of 1648);
a third level (1692) overlaying said second level (1694),
wherein said third level (1692) comprises a plurality of third transistors (of NAND string 1624),
wherein said third level (1692) comprises a fourth layer (1628), said fourth layer comprising second conductive lines (at the top of 1628); and
a plurality of connection paths (through contacts 1669/1649/1629),
wherein said plurality of connection paths (through contacts 1669/1649/1629) provides electrical connections from a plurality of said first transistors (of said first layer 1667/1606) to said plurality of third transistors (of said NAND string 1624), and
wherein said first level (10A) would have comprised at least one temperature sensor (as taught by Kawano or Sato));
referring to claim 9, the reference further discloses that said first level (1696) comprises at least one voltage regulator (851, para [179], by generator 810 of the peripheral circuit, para [178] included in the first level 1696, para [303]);
referring to claim 11, said second level (1694) is bonded to said first level (1696), wherein said bonded comprises oxide-to-oxide bond regions (the dielectric layers (not labeled, para [203]) of the first level and the second level are notoriously formed of oxide, thus forming oxide-to-oxide bond regions), wherein said bonded additionally comprises metal-to-metal bond regions (the pads, not labeled, of interconnecting layer 1668 and conductive layers, not labeled, of the second level 1694 are formed of metal, para [113]) made on a same level as said oxide-to-oxide bond regions.
referring to claim 12,
wherein said first level (1696, that includes peripheral circuit) comprises a first data bus (that electrically connect to wordline/bitline of the NAND string, para [113, 115]]),
wherein said third level (1692) comprises a second data bus (wordline/bitline of the NAND string 1624), and
wherein at least one of said connection paths (through contacts 1669/1649/1629) comprises an electrical connection between said first data bus and said second data bus.
Referring to claim 14, the reference further discloses that
said first level (1696, including peripheral circuit, para [303]) comprises at least one control circuit (row decoder, word line driver, para [126]),
said second level (1694) comprises at least one memory array (para [303]), and
that said at least one control circuit controls data written to said at least one memory array (via bit lines and word lines).
16.1. Claim 9 is rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945 and further in view of Huang et al. U.S. Patent 9,064,856 B1 or Chu et al. U.S. Patent Application Publication 20230326854.
Referring to claim 9, the ‘753 reference in view of Kawano or Sato (‘753/Kawano or ‘753/Sato) discloses a 3D semiconductor device including a first level as detailed above for claim 8, but does not disclose that said first level comprises at least one voltage regulator. However, the first level of the 3D semiconductor device requires a voltage regulator to operate or to operate safely, albeit external to the first level.
Huang, in disclosing a semiconductor device comprising a level (Fig. 1), teaches that the level comprises a voltage regulator (30, col. 3, lines 45-50) for protection of the level (col. 1, lines 5-10); or, Chu, in disclosing a semiconductor device comprising a level (200, Fig. 4), teaches that the level comprises a voltage regulator (441, para [31]) for the implied purpose of monolithically integrating the voltage regulator into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘753/Kawano’s or ‘753/Sato’s first level comprising at least one voltage regulator. One would have been motivated to make such a modification in view of the teachings in Huang for protection of the level or in view of the teachings of Chu for the implied purpose of monolithically integrating the at least one voltage regulator into the level.
16.2. Claim 10 is rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945 as detailed above for claim 8 and further in view of Azeroual U.S. Patent 8,803,339.
Referring to claim 10, the ‘753 reference in view of Kawano or Sato (‘753/Kawano or ‘753/Sato) discloses a 3D semiconductor device including a first level as detailed above for claim 8, but does not disclose said first level comprises at least one SerDes circuit. However, the first level of the 3D semiconductor device requires a SerDes circuit to operate, albeit external to the first level.
Azeroual, in disclosing a semiconductor device comprising a level (chip 100, Fig. 1A, col. 4, lines 1-8), teaches that the level comprises a SerDes (serializer/deserializer) circuit, col. 4, lines 1-8) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘753/Kawano’s or ‘753/Sato’s first level comprising at least one SerDes circuit. One would have been motivated to make such a modification in view of the teachings in Azeroual for the implied purpose of monolithically integrating the at least SerDes into the level.
16.3. Claim 13 is rejected under 35 U.S.C. §103 as being unpatentable over Zhang et al. U.S. Patent Application Publication 2024/0212753 A1 (the ‘753 reference) in view of Kawano et al. U.S. Patent Application Publication 20140061821 or Sato U.S. Patent Application Publication 20140371945 as detailed above for claim 8 and further in view of Liu et al. U.S. Patent Application Publication 20110128042.
Referring to claim 13, the ‘753 reference in view of Kawano or Sato (‘753/Kawano or ‘753/Sato) discloses a 3D semiconductor device including a first level as detailed above for claim 8, but does not disclose said first level comprises at least one PLL circuit. However, the first level of the 3D semiconductor device requires a PLL circuit to operate, albeit external to the first level.
Liu, in disclosing a semiconductor device comprising a level (chip 10, Fig. 4, para [47]), teaches that the level comprises a PLL circuit (phase lock loop circuit, para [61]) for the implied purpose of monolithically integrating the PLL into the level.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ‘753/Kawano’s or ‘753/Sato’s first level comprising at least one PLL circuit. One would have been motivated to make such a modification in view of the teachings in Liu for the implied purpose of monolithically integrating the at least PLL into the level.
Conclusion
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02-10-2025
/TU-TU V HO/Primary Examiner, Art Unit 2818