Prosecution Insights
Last updated: May 29, 2026

Monolithic 3D Inc.

8 pending office actions • 5 art units • 6 examiners • 0 of 8 (0%) have an AI response strategy ready • 31 patents granted in the last 365 days

Portfolio Summary

8
Total Pending OAs
7
Non-Final OAs
1
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 8 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

5
Overdue
0
Due this week
3
Due this month
0
Due in next 60 days
0
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 8 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (5)Due ≤ 30 days (3)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

0
Hard (0%)
4
Medium (50%)
1
Easy (12%)
3
Unknown (38%)

Rejection Statute Mix

BucketCases
§103 only3 (38%)
§102 only1 (12%)
§112 only1 (12%)
No statute on record3 (38%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
8
Semiconductors
100% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

80 h
Manual time on pending OAs
16 h
Time saved (low, 20%)
28 h
Time saved (mid, 35%)
0.7 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
KEBEDE, BROOK 2 88.8% +4.3%
WILCZEWSKI, MARY A 2 85.0% +9.9%
SALERNO, SARAH KATE 1 73.3% +14.8%
LEE, CHEUNG 1 92.2% +4.2%
VU, HUNG K 1 87.5% +9.3%
HO, TU TU V 1 93.6% +5.1%

Quick Wins (5)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
17693282 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES WILCZEWSKI, MARY A 30d overdue
19351167 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH TRANSISTORS, METAL LAYERS, AND SINGLE CRYSTAL TRANSISTOR CHANNELS KEBEDE, BROOK 8d overdue
19241517 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH CONNECTION PATHS HO, TU TU V 4d overdue
19277309 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS VU, HUNG K 14d
17679058 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES WILCZEWSKI, MARY A 29d

Interview Candidates (1)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
19349986 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH LOGIC AND MEMORY, AND A SEMICONDUCTOR DIE SALERNO, SARAH KATE 8d

Top Art Units

Art UnitApps
2818 3
2898 2
2814 1
2812 1
2897 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
19351203 METHODS OF FABRICATING 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERS AND MEMORY CELLS KEBEDE, BROOK 2818 Other Non-Final OA 2d overdue Pending Oct 06, 2025
19351167 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH TRANSISTORS, METAL LAYERS, AND SINGLE CRYSTAL TRANSISTOR CHANNELS KEBEDE, BROOK 2818 §112 Non-Final OA 8d overdue Pending Oct 06, 2025
19349986 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH LOGIC AND MEMORY, AND A SEMICONDUCTOR DIE SALERNO, SARAH KATE 2814 Other Non-Final OA 8d Pending Oct 04, 2025
19278903 METHODS FOR FABRICATING A MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH IMAGE SENSORS AND WAFER BONDING LEE, CHEUNG 2812 Other Non-Final OA 3d overdue Pending Jul 24, 2025
19277309 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS VU, HUNG K 2897 §103 Non-Final OA 14d Pending Jul 22, 2025
19241517 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH CONNECTION PATHS HO, TU TU V 2818 §103 Non-Final OA 4d overdue Pending Jun 18, 2025
17693282 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES WILCZEWSKI, MARY A 2898 §102 Non-Final OA 30d overdue Pending Mar 11, 2022
17679058 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES WILCZEWSKI, MARY A 2898 §103 Final Rejection 29d Pending Feb 23, 2022

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