Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
1. Applicant's amendments, filed May 18, 2026 are respectfully acknowledged and have been fully considered. The following rejections and/or objections are either reiterated or newly applied. They constitute the complete set presently being applied to the instant application.
Applicants have amended their claims, filed May 18, 2026 and therefore rejections newly made in the instant office action have been necessitated by amendment.
Claims 1-20 were previously cancelled. Claims 21, 26, 32, and 34 are amended. Claim 33 is cancelled..
Claims 21-32 and 34-40 are pending.
Claim Rejections - 35 USC § 112
The cancellation of Claim 33 addressing a 35 U.S.C. 112(d) issue is respectfully acknowledged, and the corresponding rejection of Claim 33 and the inherited rejections of further depending claims not mentioned are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 21, 22, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Nam et al. (U.S. Patent Application Publication 20170186826 A1, hereinafter “Nam”).
Regarding Claim 21 (Currently Amended), Park teaches a device (par 0097 Fig 15 display device) comprising:
a driving thin film transistor (TFT), the driving TFT (par 0080 Fig 1 the transistor TR according to the present exemplary embodiment can be advantageous as a driving transistor of a display device) comprising:
a driving channel (par 0060 Fig 1 semiconductor 130 includes a channel 131 that overlaps the gate electrode 124, a source region 133, and a drain region 135);
a driving inter layer dielectric (ILD) layer disposed over the driving channel (par 0075 see annotated Fig 1 below; insulation layer 160 is disposed at least partially [the portion of layer 160 indicated in light gray in the annotated Fig 1 below] above/over the driving channel 130/131);
a driving source electrode disposed through the ILD layer to contact an upper surface of the driving channel (par 0064 annotated Fig 1 below, driving source electrode 153/173 disposed through the second insulation layer 140 and ILD layer 160 to contact an upper surface of the semiconductor 130), the driving source electrode coupled to a source voltage via a source electrode path of wiring (par 0064 Fig 1 driving source electrode 153/173 coupled to a source voltage ELVDD via a source electrode path of wiring 172 [par 0101 as clearly shown in the P-type implementation of Fig 14]); and
a driving top gate electrode (par 0073 Fig 1 upper electrode 125 is a gate conductor) disposed above the driving channel (par 0074 Fig 1 semiconductor 130 overlaps the upper gate electrode 125 [Fig 1 shows top gate electrode 125 above the driving channel], interposing the second insulation layer 140 therebetween) and electrically connected to the driving source electrode (par 0078 annotated Fig 1 below, source electrode 153/173 is connected with the upper gate electrode 125 through the third contact hole 166 of the third insulation layer 160 and the gate electrode wiring path as identified in annotated Fig 1 below) and the source voltage via a top gate electrode path of wiring coupled to the source electrode path (par 0080 a source voltage, which is a voltage of the source region 133 [and electrode 153/173 and source electrode path of wiring 172], may be applied to the upper electrode 125, as shown in annotated Fig 1 below through the top gate electrode wiring path and the conductor of hole 166, coupled to source electrode path of wiring 172 at least coupled through source electrode 153/173);
a first switching TFT (par 0100 Fig 14 switching transistor Qs) comprising:
a switching channel (par 0106 Fig 14 switching n-channel).
However, Park appears not to expressly teach
a switching ILD layer disposed over the switching channel;
a switching source electrode disposed through the switching ILD layer to contact an upper surface of the switching channel, the switching source electrode coupled to a source voltage via a source electrode path of wiring; and
a switching top gate electrode disposed above the switching channel and electrically connected to a gate voltage via a switching top gate electrode path of wiring.
Nam teaches
a switching ILD layer disposed over the switching channel (par 0028 Fig 1 switching inter layer insulation/dielectric film layer 116 disposed over the switching channel);
a switching source electrode disposed through the switching ILD layer to contact an upper surface of the switching channel (par 0028 Fig 1 switching source electrode 158 disposed through the driving inter layer insulation/dielectric layer 116 at 164S to contact an upper surface of the switching channel formed in active layer 154), the switching source electrode coupled to a source voltage via a source electrode path of wiring (par 0024 Figs 1,2 switching source electrode 158 connected to the source/data voltage line DL path of wiring); and
a switching top gate electrode disposed above the switching channel (par 0024 Fig 1 switching top gate electrode 156 disposed above the switching channel formed in active layer 154) and electrically connected to a gate voltage via a switching top gate electrode path of wiring (par 0024 Figs 1,2 switching top gate electrode 156 connected to the gate/scan voltage line path of wiring).
Park and Nam are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the switching source electrode disposed through the ILD layer to contact an upper surface of the switching channel of Nam. The motivation would have been in order to provide a simplified manufacturing process and fewer source layer to layer contact interfaces for higher reliability.
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Regarding Claim 22 (Previously Presented), Park as modified teaches the device of claim 21, wherein
the first switching TFT is connected to a scan line (Park par 0102 Fig 14 switching transistor Qs is connected to the gate line 121).
Regarding Claim 24 (Previously Presented), Park as modified teaches the device of claim 21, wherein
the first switching TFT further comprises a switching drain electrode disposed through the switching ILD layer to contact the upper surface of the switching channel (Nam par 0028 Fig 1 switching drain electrode 160 disposed through the driving inter layer insulation/dielectric layer 116 at 164D to contact an upper surface of the switching channel formed in active layer 154), the switching drain electrode coupled to a drain voltage via a drain electrode path of wiring (par 0024 Figs 1,2 switching drain electrode 160 connected to the drain voltage via drain line path of wiring to the driving gate electrode 106 and to the storage lower electrode 142, par 0031).
Park and Nam are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the switching drain electrode disposed through the switching ILD layer to contact an upper surface of the switching channel of Nam. The motivation would have been in order to provide a simplified manufacturing process and fewer source layer to layer contact interfaces for higher reliability.
Regarding Claim 25 (Previously Presented), Park as modified teaches the device of claim 21, wherein
the driving TFT further comprises a driving bottom gate electrode, wherein a gate bias is applied to the driving bottom gate electrode (Park par 0060 Fig 1 a gate-on voltage is applied to the [bottom] gate electrode 124).
Claim 26, 27, and 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Ishida et al. (U.S. Patent Application 20210020662 A1, hereinafter “Ishida”).
Regarding Claim 26 (Currently Amended), Park teaches a device (par 0097 Fig 15 display device) comprising:
a driving thin film transistor (TFT), the driving TFT (par 0080 Fig 1 the transistor TR according to the present exemplary embodiment can be advantageous as a driving transistor of a display device) comprising:
a driving channel (par 0060 Fig 1 semiconductor 130 includes a channel 131 that overlaps the gate electrode 124, a source region 133, and a drain region 135);
a driving inter layer dielectric (ILD) layer disposed over the driving channel (par 0075 see annotated Fig 1 below; insulation layer 160 is disposed at least partially [the portion of layer 160 indicated in light gray in the annotated Fig 1 below] above/over the driving channel 130/131);
a driving source electrode disposed through the ILD layer to contact an upper surface of the driving channel (par 0064 annotated Fig 1 below, driving source electrode 153/173 disposed through the second insulation layer 140 and ILD layer 160 to contact an upper surface of the semiconductor 130), the driving source electrode coupled to a source voltage via a source electrode path of wiring (par 0064 Fig 1 driving source electrode 153/173 coupled to a source voltage ELVDD via a source electrode path of wiring 172 [par 0101 as clearly shown in the P-type implementation of Fig 14]); and
a driving top gate electrode (par 0073 Fig 1 upper electrode 125 is a gate conductor) disposed above the driving channel (par 0074 Fig 1 semiconductor 130 overlaps the upper gate electrode 125 [Fig 1 shows top gate electrode 125 above the driving channel], interposing the second insulation layer 140 therebetween) and electrically connected to the driving source electrode (par 0078 annotated Fig 1 below, source electrode 153/173 is connected with the upper gate electrode 125 through the third contact hole 166 of the third insulation layer 160 and the gate electrode wiring path as identified in annotated Fig 1 below) and the source voltage via a top gate electrode path of wiring coupled to the source electrode path (par 0080 a source voltage, which is a voltage of the source region 133 [and electrode 153/173 and source electrode path of wiring 172], may be applied to the upper electrode 125, as shown in annotated Fig 1 below through the top gate electrode wiring path and the conductor of hole 166, coupled to source electrode path of wiring 172 at least coupled through source electrode 153/173);
a first switching TFT (par 0100 Fig 14 switching transistor Qs) comprising:
a switching channel (par 0106 Fig 14 switching n-channel).
However, Park appears not to expressly teach
a switching ILD layer disposed over the switching channel;
a switching top gate electrode disposed above the switching channel and electrically connected to a gate voltage via a switching gate electrode path of wiring; and
a switching bottom gate electrode disposed below the switching channel and electrically connected to the gate voltage via the switching gate electrode path of wiring.
Ishida teaches
a switching ILD layer disposed over the switching channel (par 0052 Fig 4 switching interlayer insulating layer IL above channel/semiconductor layer 151);
a switching top gate electrode disposed above the switching channel (par 0052 Fig 4 switching top gate TGE above channel/semiconductor layer 151) and electrically connected to a gate voltage via a switching gate electrode path of wiring (par 0060 Fig 6 switching top gate TGE electrically connected to a gate voltage via a switching gate electrode path of wiring from switching TFT T2 and including the top gate electrode TGE to bottom gate electrode BGE connection through contact hole CBT); and
a switching bottom gate electrode disposed below the switching channel (par 0052 Fig 4 switching bottom gate BGE below switching channel/semiconductor layer 151) and electrically connected to the gate voltage via the switching gate electrode path of wiring (par 0048 Fig 4 top gate electrode TGE and the bottom gate electrode BGE are connected through the switching gate electrode path of wiring that also comprises the contact hole CBT connective path).
Park and Ishida are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the switching drain electrode disposed through the switching ILD layer to contact an upper surface of the switching channel of Ishida. The motivation would have been in order to provide suppression of variations of a threshold voltage in a negative direction since the first gate electrode is superimposed over the oxide semiconductor layer with the metal oxide layer interposed between the first gate electrode and the oxide semiconductor layer (Ishida par 0006).
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Regarding Claim 27 (Previously Presented), Park as modified teaches the device of claim 26, wherein
the first switching TFT is connected to a scan line (Park par 0102 Fig 14 switching transistor Qs is connected to the gate line 121).
Regarding Claim 29 (Previously Presented), Park as modified teaches the device of claim 26, wherein
the first switching TFT further comprises:
a switching source electrode disposed through the switching ILD layer to contact an upper surface of the switching channel (Ishida par 0052 Fig 4 the [switching] source electrode SE is electrically connected to a source region [upper side of the channel] of the oxide semiconductor layer through a contact hole formed in the interlayer insulating layer IL), the switching source electrode coupled to a source voltage via a source electrode path of wiring (par 0060 Fig 6 switching source electrode SE electrically connected to a source voltage via a switching source electrode path of wiring e.g. to the driving gate electrode).
Park and Ishida are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the switching drain electrode disposed through the switching ILD layer to contact an upper surface of the switching channel of Ishida. The motivation would have been in order to provide suppression of variations of a threshold voltage in a negative direction since the first gate electrode is superimposed over the oxide semiconductor layer with the metal oxide layer interposed between the first gate electrode and the oxide semiconductor layer (Ishida par 0006).
Regarding Claim 30 (Previously Presented), Park as modified teaches the device of claim 26, wherein
the first switching TFT further comprises a switching drain electrode disposed through the switching ILD layer to contact the upper surface of the switching channel (Ishida par 0052 Fig 4 the [switching] drain electrode DE is electrically connected to a drain region [upper side of the channel] of the oxide semiconductor layer through a contact hole formed in the interlayer insulating layer IL), the switching drain electrode coupled to a drain voltage via a drain electrode path of wiring (par 0060 Fig 6 switching drain electrode DE electrically connected to a drain voltage via a switching drain electrode path of wiring e.g. S(m)).
Park and Ishida are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the switching drain electrode disposed through the switching ILD layer to contact an upper surface of the switching channel of Ishida. The motivation would have been in order to provide suppression of variations of a threshold voltage in a negative direction since the first gate electrode is superimposed over the oxide semiconductor layer with the metal oxide layer interposed between the first gate electrode and the oxide semiconductor layer (Ishida par 0006).
Regarding Claim 31 (Previously Presented), Park as modified teaches the device of claim 26, wherein
the device comprises a pixel circuit (Park par 0099 Fig 14 the display device comprises a pixel/subpixel circuit, shown).
Claim 32, 35-37, and 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Lius et al. (U.S. Patent Application 20170294497 A1, hereinafter “Lius”).
Regarding Claim 32 (Currently Amended), Park teaches a device (par 0097 Fig 15 display device) comprising:
a driving thin film transistor (TFT), the driving TFT (par 0080 Fig 1 the transistor TR according to the present exemplary embodiment can be advantageous as a driving transistor of a display device) comprising:
a driving channel (par 0060 Fig 1 semiconductor 130 includes a channel 131 that overlaps the gate electrode 124, a source region 133, and a drain region 135);
a driving inter layer dielectric (ILD) layer disposed over the driving channel (par 0075 see annotated Fig 1 below; insulation layer 160 is disposed at least partially [the portion of layer 160 indicated in light gray in the annotated Fig 1 below] above/over the driving channel 130/131);
a driving source electrode disposed through the ILD layer to contact an upper surface of the driving channel (par 0064 annotated Fig 1 below, driving source electrode 153/173 disposed through the second insulation layer 140 and ILD layer 160 to contact an upper surface of the semiconductor 130), the driving source electrode coupled to a source voltage via a source electrode path of wiring (par 0064 Fig 1 driving source electrode 153/173 coupled to a source voltage ELVDD via a source electrode path of wiring 172 [par 0101 as clearly shown in the P-type implementation of Fig 14]); and
a driving top gate electrode (par 0073 Fig 1 upper electrode 125 is a gate conductor) disposed above the driving channel (par 0074 Fig 1 semiconductor 130 overlaps the upper gate electrode 125 [Fig 1 shows top gate electrode 125 above the driving channel], interposing the second insulation layer 140 therebetween) and electrically connected to the driving source electrode (par 0078 annotated Fig 1 below, source electrode 153/173 is connected with the upper gate electrode 125 through the third contact hole 166 of the third insulation layer 160 and the gate electrode wiring path as identified in annotated Fig 1 below) and the source voltage via a top gate electrode path of wiring coupled to the source electrode path (par 0080 a source voltage, which is a voltage of the source region 133 [and electrode 153/173 and source electrode path of wiring 172], may be applied to the upper electrode 125, as shown in annotated Fig 1 below through the top gate electrode wiring path and the conductor of hole 166, coupled to source electrode path of wiring 172 at least coupled through source electrode 153/173);
a first switching TFT (par 0100 Fig 14 switching transistor Qs) connected to a scan line (Park par 0102 Fig 14 switching transistor Qs is connected to the gate line 121).
However, Park appears not to expressly teach
the switching TFT comprising:
a first switching TFT comprising:
a first TFT comprising:
a first channel;
a gate insulator layer disposed below the first channel, and a first top gate electrode disposed above the first channel; and
a second TFT adjacent to the first TFT comprising:
a second channel;
the gate insulator layer disposed below the second channel;
a second top gate electrode disposed above the second channel, wherein
the gate insulator layer extends from the first TFT and is disposed between the second channel and a bottom gate electrode.
Lius teaches
the switching TFT comprising:
a first switching TFT (par 0058 Fig 5 switching TFT T2) comprising:
a first TFT comprising:
a first channel (par 0058 Fig 5 channel of first semiconductor region 221);
a gate insulator layer disposed below the first channel (par 0058 Fig 5 gate insulator layer 101 [par 0046] disposed below channel of first semiconductor region 221), and a first top gate electrode disposed above the first channel (par 0058 Fig 5 first top gate electrode 251 disposed above the first channel of first semiconductor region 221); and
a second TFT adjacent to the first TFT (Fig 5 at adjacent gates 251,252) comprising:
a second channel (par 0058 Fig 5 channel of second semiconductor region 222);
the gate insulator layer disposed below the second channel (par 0058 Fig 5 gate insulator layer 101 [par 0046] disposed below channel of second semiconductor region 222);
a second top gate electrode disposed above the second channel (par 0058 Fig 5 second top gate electrode 252 disposed above the second channel of second semiconductor region 222), wherein
the gate insulator layer extends from the first TFT and is disposed between the second channel and a bottom gate electrode (par 0058 Fig 5 the gate insulator layer 101 extends from the first TFT [at semiconductor region 221] and is disposed between the second channel [of semiconductor region 222] and a bottom gate electrode 11 of TFT T1).
Park and Lius are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the double gate switching transistor of Lius. The motivation would have been in order to provide improved ON current or electron charging speed of the first transistor (Lius par 0009).
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Regarding Claim 35 (Previously Presented), Park as modified teaches the device of claim 32, wherein
at least one of the first channel and the second channel is a metal oxide containing layer comprising at least one of indium, zinc, gallium, oxygen, aluminum, tin, In-Zn-O, In-Sn-O, In-Zn-Sn-O, In-Ga-O, In-Ga-Zn-O, In- Ga-Sn-O, In-Ga-Zn-Sn-O, or a combination thereof (Lius par 0055 Fig 5 switching transistor T2 is an IGZO TFT with both channels IGZO).
Park and Lius are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the double gate switching transistor of Lius. The motivation would have been in order to provide improved ON current or electron charging speed of the first transistor (Lius par 0009).
Regarding Claim 36 (Previously Presented), Park as modified teaches the device of claim 32, wherein
at least one of the first channel and the second channel is a low temperature poly silicon (LTPS) single layer (Lius paras 0055,67 Fig 8 switching transistor T2 is a LTPS TFT with both channels LTPS single layer).
Park and Lius are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the double gate switching transistor of Lius. The motivation would have been in order to provide improved ON current or electron charging speed of the first transistor (Lius par 0009).
Regarding Claim 37 (Previously Presented), Park as modified teaches the device of claim 32, wherein
at least one of the first channel or the second channel, or both the first and second channel each consist of a single layer (Lius paras 0055,67 Fig 8 switching transistor T2 is a LTPS TFT with both channels LTPS single layer).
Regarding Claim 39 (Previously Presented), Park as modified teaches the device of claim 32, wherein
the device comprises a pixel circuit (Park par 0099 Fig 14 the display device comprises a pixel/subpixel circuit, shown).
Regarding Claim 40 (Previously Presented), Park as modified teaches the device of claim 32, wherein
the ILD layer extends across an upper surface of the first top gate electrode and the second top gate electrode (par 0058 Fig 5 the ILD layer 102 [par 0043] extends across an upper surface of the first top gate electrode 251 and the second top gate electrode 255).
Park and Lius are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the double gate switching transistor of Lius. The motivation would have been in order to provide improved ON current or electron charging speed of the first transistor (Lius par 0009).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Nam et al. (U.S. Patent Application Publication 20170186826 A1, hereinafter “Nam”) and further in view of Shang et al. (U.S. Patent Application 20210090484 A1, hereinafter “Shang”).
Regarding Claim 23 (Previously Presented), Park as modified teaches the device of claim 22. However, Park as modified appears not to expressly teach further comprising:
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT, wherein
the second switching TFT and the third switching TFT are connected to the scan line.
Shang teaches
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT (paras 0396-0407 Figs 24,26 Shang proposes several switching transistors of a GOA circuit may include the top and bottom gate structure), wherein
the second switching TFT and the third switching TFT are connected to the scan line (par 0400-0401 the output control transistor and the output pull-down transistor, both connected to the gate/scan output line, may include the top and bottom gate structure).
Park Nam and Shang are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park/Nam with the inclusion of the switching TFT gate GOA arrangement of Shang. The motivation would have been in order to provide a structure with less leakage current in the switching transistor (Shang par 0399).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Ishida et al. (U.S. Patent Application 20210020662 A1, hereinafter “Ishida”) and further in view of Shang et al. (U.S. Patent Application 20210090484 A1, hereinafter “Shang”).
Regarding Claim 28 (Previously Presented), Park as modified teaches the device of claim 27. However, Park as modified appears not to expressly teach further comprising:
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT, wherein
the second switching TFT and the third switching TFT are connected to the scan line.
Shang teaches
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT (paras 0396-0407 Figs 24,26 Shang proposes several switching transistors of a GOA circuit may include the top and bottom gate structure), wherein
the second switching TFT and the third switching TFT are connected to the scan line (par 0400-0401 the output control transistor and the output pull-down transistor, both connected to the gate/scan output line, may include the top and bottom gate structure).
Park Ishida and Shang are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park/Ishida with the inclusion of the switching TFT gate GOA arrangement of Shang. The motivation would have been in order to provide a structure with less leakage current in the switching transistor (Shang par 0399).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Lius et al. (U.S. Patent Application 20170294497 A1, hereinafter “Lius”) and further in view of Shang et al. (U.S. Patent Application 20210090484 A1, hereinafter “Shang”).
Regarding Claim 34 (Currently Amended), Park as modified teaches the device of claim 32. However, Park as modified appears not to expressly teach further comprising:
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT, wherein
the second switching TFT and the third switching TFT are connected to the scan line.
Shang teaches
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT (paras 0396-0407 Figs 24,26 Shang proposes several switching transistors of a GOA circuit may include the top and bottom gate structure), wherein
the second switching TFT and the third switching TFT are connected to the scan line (par 0400-0401 the output control transistor and the output pull-down transistor, both connected to the gate/scan output line, may include the top and bottom gate structure).
Park Lius and Shang are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park/Lius with the inclusion of the switching TFT gate GOA arrangement of Shang. The motivation would have been in order to provide a structure with less leakage current in the switching transistor (Shang par 0399).
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Application Publication 20170338248 A1) in view of Lius et al. (U.S. Patent Application 20170294497 A1, hereinafter “Lius”) and further in view of Lee et al. (U.S. Patent Application 20220278234 A1, hereinafter “Lee”)
Regarding Claim 38 (Previously Presented), Park as modified teaches the device of claim 32. However, Park as modified appears not to expressly teach wherein
at least one of the first channel or the second channel comprise two or more layers, each layer having different electron mobility.
Lee teaches wherein
at least one of the first channel or the second channel comprise two or more layers (par 0037 Fig 1 active layer 130 may be formed in a plurality of metal oxide thin film [layers] which are formed in a plurality of metal oxide thin films including a first metal oxide thin film 130a, a second metal oxide thin film 130b, and a third metal oxide thin film 130c), each layer having different electron mobility (paras 0039,0040 Fig 1 first oxide film layer 130a has a high mobility, while second oxide film layer 130b has a relatively low conductivity and thus low mobility).
Park Lius and Lee are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Park/Lius with the inclusion of the multilayer channel arrangement of Lee. The motivation would have been in order to provide improved stability while having high mobility (Lee par 0006).
Response to Arguments
Applicant's arguments filed May 18, 2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to independent claims 21, 26, and 32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK EDWARDS whose telephone number is 571-270-7731. The examiner can normally be reached on M-F 9a-5p.
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/MARK EDWARDS/
Primary Examiner, Art Unit 2624
Prosecution Insights