Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Preliminary Amendment
1. Applicant's amendments, filed September 11, 2025 are respectfully acknowledged and have been fully considered.
Claims 1-20 are cancelled. Claims 21-40 are newly added.
Claims 21-40 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 33 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
The Claim 33 limitation “the first switching TFT is connected to a scan line” simply repeats the limitation of Claim 32 line 8 “a first switching TFT connected to a scan line”.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Further depending claims not mentioned inherit the deficiencies of their respective base claims and are rejected [objected to] under similar rationale.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21, 22, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam et al. (U.S. Patent Application Publication 20170186826 A1, hereinafter “Nam”).
Regarding Claim 21 (New), Nam teaches a device (par 0022 Fig 1 display device) comprising:
a driving thin film transistor (TFT), the driving TFT (par 0023 Fig 1 driving transistor 100) comprising:
a driving channel (paras 0025,0027 Fig 1 driving channel formed in active layer 104 between source 108 and drain 110);
a driving inter layer dielectric (ILD) layer disposed over the driving channel (par 0028 Fig 1 driving inter layer insulation/dielectric film layer 116 disposed over the driving channel);
a driving source electrode disposed through the ILD layer to contact an upper surface of the driving channel (par 0028 Fig 1 driving source electrode 108 disposed through the driving inter layer insulation/dielectric layer 116 to contact an upper surface of the driving channel formed in active layer 104); and
a driving top gate electrode disposed above the driving channel (par 0025 Fig 1 driving top gate electrode 106 disposed above the driving channel formed in active layer 104);
a first switching TFT (par 0023 Fig 1 switching transistor 150) comprising:
a switching channel (par 0027 Fig 1 switching channel formed in active layer 154 between source 158 and drain 160);
a switching ILD layer disposed over the switching channel (par 0028 Fig 1 switching inter layer insulation/dielectric film layer 116 disposed over the switching channel);
a switching source electrode disposed through the switching ILD layer to contact an upper surface of the switching channel (par 0028 Fig 1 switching source electrode 158 disposed through the driving inter layer insulation/dielectric layer 116 at 164S to contact an upper surface of the switching channel formed in active layer 154), the switching source electrode coupled to a source voltage via a source electrode path of wiring (par 0024 Figs 1,2 switching source electrode 158 connected to the source/data voltage line DL path of wiring); and
a switching top gate electrode disposed above the switching channel (par 0024 Fig 1 switching top gate electrode 156 disposed above the switching channel formed in active layer 154) and electrically connected to a gate voltage via a switching top gate electrode path of wiring (par 0024 Figs 1,2 switching top gate electrode 156 connected to the gate/scan voltage line path of wiring).
Regarding Claim 22 (New), Nam teaches the device of claim 21, wherein
the first switching TFT is connected to a scan line (par 0024 Figs 1,2 switching top gate electrode 156 of switching transistor 150 is connected to the gate/scan voltage line path of wiring).
Regarding Claim 24 (New), Nam teaches the device of claim 21, wherein
the first switching TFT further comprises a switching drain electrode disposed through the switching ILD layer to contact the upper surface of the switching channel (par 0028 Fig 1 switching drain electrode 160 disposed through the driving inter layer insulation/dielectric layer 116 at 164D to contact an upper surface of the switching channel formed in active layer 154), the switching drain electrode coupled to a drain voltage via a drain electrode path of wiring (par 0024 Figs 1,2 switching drain electrode 160 connected to the drain voltage via drain line path of wiring to the driving gate electrode 106 and to the storage lower electrode 142, par 0031).
Claim 26, 27, and 29-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishida et al. (U.S. Patent Application 20210020662 A1, hereinafter “Ishida”).
Regarding Claim 26 (New), Ishida teaches a device (par 0020 Fig 2 display device 2) comprising:
a driving thin film transistor (TFT) (par 0060 Fig 6 driving TFT T1), the driving TFT comprising:
a driving channel (paras 0055,0098 Fig 4 driving channel in semiconductor layer 151);
a driving inter layer dielectric (ILD) layer disposed over the driving channel (par 0052 Fig 4 driving interlayer insulating layer IL above channel/semiconductor layer 151);
a driving source electrode disposed through the driving ILD layer to contact an upper surface of the driving channel (par 0052 Fig 4 the [driving] source electrode SE is electrically connected to a source region [upper side of the channel] of the oxide semiconductor layer through a contact hole formed in the interlayer insulating layer IL); and
a driving top gate electrode disposed above the driving channel (par 0052 Fig 4 driving top gate TGE above channel/semiconductor layer 151);
a first switching TFT (par 0060 Fig 6 switching TFT T2) comprising:
a switching channel (paras 0055,0098 Fig 4 switching channel in semiconductor layer 151);
a switching ILD layer disposed over the switching channel (par 0052 Fig 4 switching interlayer insulating layer IL above channel/semiconductor layer 151);
a switching top gate electrode disposed above the switching channel (par 0052 Fig 4 switching top gate TGE above channel/semiconductor layer 151) and electrically connected to a gate voltage via a switching gate electrode path of wiring (par 0060 Fig 6 switching top gate TGE electrically connected to a gate voltage via a switching gate electrode path of wiring from switching TFT T2 and including the top gate electrode TGE to bottom gate electrode BGE connection through contact hole CBT); and
a switching bottom gate electrode disposed below the switching channel (par 0052 Fig 4 switching bottom gate BGE below switching channel/semiconductor layer 151) and electrically connected to the gate voltage via the switching gate electrode path of wiring (par 0048 Fig 4 top gate electrode TGE and the bottom gate electrode BGE are connected through the switching gate electrode path of wiring that also comprises the contact hole CBT connective path).
Regarding Claim 27 (New), Ishida teaches the device of claim 26, wherein
the first switching TFT is connected to a scan line (par 0024 Figs 4,6 switching transistor 150 is connected to the gate/scan voltage line G(n)).
Regarding Claim 29 (New), Ishida teaches the device of claim 26, wherein
the first switching TFT further comprises:
a switching source electrode disposed through the switching ILD layer to contact an upper surface of the switching channel (par 0052 Fig 4 the [switching] source electrode SE is electrically connected to a source region [upper side of the channel] of the oxide semiconductor layer through a contact hole formed in the interlayer insulating layer IL), the switching source electrode coupled to a source voltage via a source electrode path of wiring (par 0060 Fig 6 switching source electrode SE electrically connected to a source voltage via a switching source electrode path of wiring e.g. to the driving gate electrode).
Regarding Claim 30 (New), Ishida teaches the device of claim 26, wherein
the first switching TFT further comprises a switching drain electrode disposed through the switching ILD layer to contact the upper surface of the switching channel (par 0052 Fig 4 the [switching] drain electrode DE is electrically connected to a drain region [upper side of the channel] of the oxide semiconductor layer through a contact hole formed in the interlayer insulating layer IL), the switching drain electrode coupled to a drain voltage via a drain electrode path of wiring (par 0060 Fig 6 switching drain electrode DE electrically connected to a drain voltage via a switching drain electrode path of wiring e.g. S(m)).
Regarding Claim 31 (New), Ishida teaches the device of claim 26, wherein
the device comprises a pixel circuit (par 0060 Fig 6 display device 2 comprises a pixel/subpixel circuit).
Claim 32-33, 35-37, and 39-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lius et al. (U.S. Patent Application 20170294497 A1, hereinafter “Lius”).
Regarding Claim 32 (New), Lius teaches a device (par 0033 Fig 1 display device) comprising:
a driving thin film transistor (TFT) (par 0034 Fig 2 driving TFT T1), the driving TFT comprising:
a driving channel (par 0048 Fig 13 driving channel in semiconductor layer 12);
a driving inter layer dielectric (ILD) layer disposed over the driving channel (paras 0043,0098 Fig 13 the [driving] insulating layer 102 disposed over the channel of semiconductor 12);
a driving source electrode disposed through the ILD layer to contact an upper surface of the driving channel (paras 0043,0098 Fig 13 the [driving] source electrode 13 is electrically connected to a source region [upper side of the channel] of the oxide semiconductor layer 12 through the insulating layer 102); and
a driving top gate electrode disposed above the driving channel (par 0048 Fig 13 driving top gate 15 above channel/semiconductor layer 12);
a first switching TFT connected to a scan line (par 0034 Figs 2,5 switching TFT T2 connected to scan line Sn);
the switching TFT comprising:
a first switching TFT (par 0058 Fig 5 switching TFT T2) comprising:
a first TFT comprising:
a first channel (par 0058 Fig 5 channel of first semiconductor region 221);
a gate insulator layer disposed below the first channel (par 0058 Fig 5 gate insulator layer 101 [par 0046] disposed below channel of first semiconductor region 221), and a first top gate electrode disposed above the first channel (par 0058 Fig 5 first top gate electrode 251 disposed above the first channel of first semiconductor region 221); and
a second TFT adjacent to the first TFT (Fig 5 at adjacent gates 251,252) comprising:
a second channel (par 0058 Fig 5 channel of second semiconductor region 222);
the gate insulator layer disposed below the second channel (par 0058 Fig 5 gate insulator layer 101 [par 0046] disposed below channel of second semiconductor region 222);
a second top gate electrode disposed above the second channel (par 0058 Fig 5 second top gate electrode 252 disposed above the second channel of second semiconductor region 222), wherein
the gate insulator layer extends from the first TFT and is disposed between the second channel and a bottom gate electrode (par 0058 Fig 5 the gate insulator layer 101 extends from the first TFT [at semiconductor region 221] and is disposed between the second channel [of semiconductor region 222] and a bottom gate electrode 11 of TFT T1).
Regarding Claim 33 (New), Lius teaches the device of claim 32, wherein
the first switching TFT is connected to a scan line (par 0034 Figs 2,5 switching TFT T2 connected to scan line Sn).
Regarding Claim 35 (New), Lius teaches the device of claim 32, wherein
at least one of the first channel and the second channel is a metal oxide containing layer comprising at least one of indium, zinc, gallium, oxygen, aluminum, tin, In-Zn-O, In-Sn-O, In-Zn-Sn-O, In-Ga-O, In-Ga-Zn-O, In- Ga-Sn-O, In-Ga-Zn-Sn-O, or a combination thereof (par 0055 Fig 5 switching transistor T2 is an IGZO TFT with both channels IGZO).
Regarding Claim 36 (New), Lius teaches the device of claim 32, wherein
at least one of the first channel and the second channel is a low temperature poly silicon (LTPS) single layer (paras 0055,67 Fig 8 switching transistor T2 is a LTPS TFT with both channels LTPS single layer).
Regarding Claim 37 (New), Lius teaches the device of claim 32, wherein
at least one of the first channel or the second channel, or both the first and second channel each consist of a single layer (paras 0055,67 Fig 8 switching transistor T2 is a LTPS TFT with both channels LTPS single layer).
Regarding Claim 39 (New), Lius teaches the device of claim 32, wherein
the device comprises a pixel circuit (par 0034 Fig 2 the display device comprises a pixel circuit).
Regarding Claim 40 (New), Lius teaches the device of claim 32, wherein
the ILD layer extends across an upper surface of the first top gate electrode and the second top gate electrode (par 0058 Fig 5 the ILD layer 102 [par 0043] extends across an upper surface of the first top gate electrode 251 and the second top gate electrode 255).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (U.S. Patent Application Publication 20170186826 A1, hereinafter “Nam”) in view of Shang et al. (U.S. Patent Application 20210090484 A1, hereinafter “Shang”).
Regarding Claim 23 (New), Nam teaches the device of claim 22. However, Nam appears not to expressly teach further comprising:
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT, wherein
the second switching TFT and the third switching TFT are connected to the scan line.
Shang teaches
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT (paras 0396-0407 Figs 24,26 Shang proposes several switching transistors of a GOA circuit may include the top and bottom gate structure), wherein
the second switching TFT and the third switching TFT are connected to the scan line (par 0400-0401 the output control transistor and the output pull-down transistor, both connected to the gate/scan output line, may include the top and bottom gate structure).
Nam and Shang are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Nam with the inclusion of the switching TFT gate GOA arrangement of Shang. The motivation would have been in order to provide a structure with less leakage current in the switching transistor (Shang par 0399).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (U.S. Patent Application Publication 20170186826 A1, hereinafter “Nam”) in view of Park (U.S. Patent Application Publication 20170338248 A1).
Regarding Claim 25 (New), Nam teaches the device of claim 21. However, Nam appears not to expressly teach wherein
the driving TFT further comprises a driving bottom gate electrode, wherein a gate bias is applied to the driving bottom gate electrode.
Park teaches wherein
the driving TFT further comprises a driving bottom gate electrode, wherein a gate bias is applied to the driving bottom gate electrode (Park par 0060 Fig 1 a gate-on voltage is applied to the [bottom] gate electrode 124).
Nam and Park are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Nam with the inclusion of the driving bottom gate electrode of Park. The motivation would have been in order to provide that when a gate-on voltage is applied to the gate electrode 124, the source area 133 and the drain region 135 may be determined depending on a direction of carriers that flow through the channel 131, and the carriers flow to the drain electrode 135 from the source region 133; and the gate electrode may also act as a light blocking film to prevent characteristic deterioration of the semiconductor 130 and control a leakage current of the transistor (Park paras 0060-0061).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Ishida et al. (U.S. Patent Application 20210020662 A1, hereinafter “Ishida”) in view of Shang et al. (U.S. Patent Application 20210090484 A1, hereinafter “Shang”).
Regarding Claim 28 (New), Ishida teaches the device of claim 27. However, Ishida appears not to expressly teach further comprising:
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT, wherein
the second switching TFT and the third switching TFT are connected to the scan line.
Shang teaches
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT (paras 0396-0407 Figs 24,26 Shang proposes several switching transistors of a GOA circuit may include the top and bottom gate structure), wherein
the second switching TFT and the third switching TFT are connected to the scan line (par 0400-0401 the output control transistor and the output pull-down transistor, both connected to the gate/scan output line, may include the top and bottom gate structure).
Ishida and Shang are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Ishida with the inclusion of the switching TFT gate GOA arrangement of Shang. The motivation would have been in order to provide a structure with less leakage current in the switching transistor (Shang par 0399).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Lius et al. (U.S. Patent Application 20170294497 A1, hereinafter “Lius”) in view of Shang et al. (U.S. Patent Application 20210090484 A1, hereinafter “Shang”).
Regarding Claim 34 (New), Lius teaches the device of claim 33. However, Lius appears not to expressly teach further comprising:
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT, wherein
the second switching TFT and the third switching TFT are connected to the scan line.
Shang teaches
a gate on array (GOA) circuit, the GOA circuit comprising a second switching TFT and a third switching TFT (paras 0396-0407 Figs 24,26 Shang proposes several switching transistors of a GOA circuit may include the top and bottom gate structure), wherein
the second switching TFT and the third switching TFT are connected to the scan line (par 0400-0401 the output control transistor and the output pull-down transistor, both connected to the gate/scan output line, may include the top and bottom gate structure).
Lius and Shang are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Lius with the inclusion of the switching TFT gate GOA arrangement of Shang. The motivation would have been in order to provide a structure with less leakage current in the switching transistor (Shang par 0399).
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Lius et al. (U.S. Patent Application 20170294497 A1, hereinafter “Lius”) in view of Lee et al. (U.S. Patent Application 20220278234 A1, hereinafter “Lee”)
Regarding Claim 38 (New), Lius teaches the device of claim 32. However, Lius appears not to expressly teach wherein
at least one of the first channel or the second channel comprise two or more layers, each layer having different electron mobility.
Lee teaches wherein
at least one of the first channel or the second channel comprise two or more layers (par 0037 Fig 1 active layer 130 may be formed in a plurality of metal oxide thin film [layers] which are formed in a plurality of metal oxide thin films including a first metal oxide thin film 130a, a second metal oxide thin film 130b, and a third metal oxide thin film 130c), each layer having different electron mobility (paras 0039,0040 Fig 1 first oxide film layer 130a has a high mobility, while second oxide film layer 130b has a relatively low conductivity and thus low mobility).
Lius and Lee are analogous art as they each pertain to devices comprising driving thin film transistors. It would have been obvious to a person of ordinary skill in the art to modify the device of Lius with the inclusion of the multilayer channel arrangement of Lee. The motivation would have been in order to provide improved stability while having high mobility (Lee par 0006).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK EDWARDS whose telephone number is 571-270-7731. The examiner can normally be reached on M-F 9a-5p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARK EDWARDS/
Primary Examiner, Art Unit 2624