DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Initially it should be noted that this application is a continuation of Application 18/377,723, filed October 6, 2023, now USP 12,360,864, which is a continuation of
17/674,392, filed February 17, 2023, now USP 11,782,806, which is a continuation of
16/703,192, filed December 4, 2019, now USP 11,288,145,
having the same Assignee and inventor.
Claims 1 and 20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 12 of U.S. Patent No. 11,288,145. Although the conflicting claims are not identical, they are not patentably distinct from each other because of the following:
For claim 1, U.S. 11,288,145 claim 12 recites essentially similar limitations as demonstrated by the following table:
Instant Application
U.S. 11,288,145
comments
1. A graphics processing system comprising:
1. A graphics processing system comprising:
same
cache configured for holding tasks of a first type;
B
a plurality of processing units,
a plurality of processing units
same
configured for processing tasks,
wherein the graphics processing system is configured to process
wherein the graphics processing system is configured to process
same
each task of the first type first and second times at the plurality of processing units so as to, respectively, generate first and second processed outputs,
each task of a first type first and second times at the plurality of processing units so as to, respectively, generate first and second processed outputs;
same
and wherein a task of the first type is not removed from the cache when a processing unit of the plurality of processing units retrieves that task for processing for a first time;
A
and a fault detection unit configured to raise a fault signal if the first and second processed outputs do not match.
and a fault detection unit configured to raise a fault signal if the first and second processed outputs do not match;
same
wherein data is maintained identifying which processing units of the plurality of processing units each task has been allocated to, wherein said data is consulted on allocating a task of the first type to a processing unit for processing for a second time, and, in response, that task is allocated for processing for the second time to any processing unit of the plurality of processing units other than the processing unit to which that task was allocated for processing for a first time.
12. The graphics processing system as claimed in claim 1, further comprising
a cache for holding tasks of the first type
Similar to B
for processing at the plurality of processing units,
wherein a task of the first type is not removed from the cache when a processing unit retrieves that task for processing for a first time.
Similar to A
For claim 20, the claims recite essentially similar limitations as patent claim 12, except that claim 20 is a medium.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3, 11, and 16-17 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
For claim 3, the phrase ”The graphics processing system as claimed in claim 1, the graphics processing system further comprising” is syntactically incorrect and thus indefinite. It is suggested it be amended to “The graphics processing system as claimed in claim 1, [[the graphics processing system]] further comprising”.
For claim 11, the term ”the same” lacks sufficient antecedent basis in the claim. It is suggested it be amended to “[[the]] a same”.
For claim 17, the phrase ”wherein the plurality of processing units, check unit and fault detection unit are provided” is syntactically incorrect and thus indefinite. It is suggested it be amended to “wherein the plurality of processing units, the check unit [[and]] , and the fault detection unit are provided”.
For claim 17, the term ”the check unit” is indefinite because two instances of “check unit” were declared earlier, and so it is unclear to which the claim refers to. Amending claim 17 to the previous suggestion (“wherein the plurality of processing units, the check unit [[and]], and the fault detection unit are provided”) will resolve the issue.
Dependent claims inherit rejections.
Allowable Subject Matter
Claims 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and all 35 USC § 112 and Double Patenting rejections are overcome.
Reasons for Allowability
For dependent claims 16-17,
The claims are allowable because although prior art has been found to teach using signatures which are a function of outputs for fast comparison for error detection, no prior art was found to teach further steps of signature calculations and comparison (which will introduce delays) for the error detection, as it pertains to the other portions of the claim, in a manner that would motivate a person of ordinary skill in the art to combine it as an obvious inclusion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-15, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vera (US 2009/0113240 A1).
For claim 1, Vera teaches a graphics processing system comprising: (see paragraph [0037]: system contains graphics engine and port thus it is considered a graphics system) a cache configured for holding tasks of a first type (see [0024]: unified cache hold instructions; view instructions as said tasks); a plurality of processing units, wherein the graphics processing system is configured to process each task (see [0023]: view multi-core as said plurality) of the first type first and second times at the plurality of processing units so as to, respectively, generate first and second processed outputs (see [0011]), and wherein a task of the first type is not removed from the cache when a processing unit of the plurality of processing units retrieves that task for processing for a first time (see figure 1, [0011], [0013], [0017], view instruction does not leave pipeline until it’s retired, as said not removed from cache); and a fault detection unit configured to raise a fault signal if the first and second processed outputs do not match (see [0011] and other locations pointed to above).
For claims 19-20, the claim recites essentially similar limitations as claim 1. Claim 19 is a method and claim 20 is a medium. Both processing units are cores of multi-core processor.
For claim 2, Vera teaches the limitations of claim 1 for the reasons above and further teaches each processing unit of the plurality of processing units is configured to process a task independently from any other processing unit of the plurality of processing units (see [0023]: each core has its own stream of instructions).
For claim 4, Vera teaches the limitations of claim 1 for the reasons above and further teaches each task of a second type is processed only a first time at the plurality of processing units so as to generate a respective single processed output (see figure 1 and related paragraphs: only vulnerable instructions are re-executed).
For claim 5, Vera teaches the limitations of claim 4 for the reasons above and further teaches the graphics processing system is configured to concurrently process tasks of the first and second type at different processing units of the plurality of processing units of the graphics processing system (see [0036]: all processors and core process may include vulnerable instructions).
For claim 6, Vera teaches the limitations of claim 4 for the reasons above and further teaches each task of the second type is a non-safety task which is not to be processed according to a predefined safety level (see figure 1 and [0036]: view vulnerable/not vulnerable as said safety/non-safety).
For claim 7, Vera teaches the limitations of claim 1 for the reasons above and further teaches one or more other processing units configured to process tasks of a second type, the one or more other processing units being configured to process each task of the second type only a first time (see [0036] many processors including cores may have vulnerable instructions/tasks, Not re-executed).
For claim 8, Vera teaches the limitations of claim 1 for the reasons above and further teaches each task of the first type is a safety task which is to be processed according to a predefined safety level (see figure 1 and [0036]: view vulnerable/not vulnerable as said safety/non-safety).
For claim 9, Vera teaches the limitations of claim 1 for the reasons above and further teaches a first processing unit of the plurality of processing units is configured to process a task of the first type on the first time of processing, and a second processing unit of the plurality of processing units is configured to process that task of the first type on the second time of processing (see rejection to claim 4: this can occur if both processors are same).
For claim 10, Vera teaches the limitations of claim 9 for the reasons above and further teaches the graphics processing system is configured such that the second processing unit receives that task of the first type independently to the first processing unit (see [0023, [0036]: each core has its own stream of instructions which may be vulnerable).
For claim 11, Vera teaches the limitations of claim 9 for the reasons above and further teaches the graphics processing system is configured such that: the second processing unit is constrained to be any processing unit of the plurality of processing units other than the first processing unit; or the first and second processing units are permitted to be the same processing unit (see locations and explanations pointed to in rejection to claim 9).
For claim 12, Vera teaches the limitations of claim 9 for the reasons above and further teaches the graphics processing system includes an allocation unit configured to allocate tasks of the first type to the first and second processing units (see [0046]).
For claim 13, Vera teaches the limitations of claim 1 for the reasons above and further teaches each task of the first type includes an identifier having a least two states: an initial state indicating that a task of the first type has not been processed for a first time, and a second state indicating that a task of the first type has been processed for a first time, and wherein each processing unit of the plurality of processing units is configured to, on processing a task of the first type for a first time, update the identifier from the initial state to the second state (see [0017], figure 1: view status of instruction as said identifier, or vulnerability initial condition value vs. calculated value).
For claim 14, Vera teaches the limitations of claim 13 for the reasons above and further teaches a particular processing unit of the plurality of processing units is configured to, on accessing the cache, retrieve a task of a first type (see [0024]: instruction in unified cache is for executing) having an identifier in the second state only if that particular processing unit did not process that task when processed for a first time (see [0017]: that particular processing unit did not process that task for a second time when processed for a first time (when underline added, it describes same situation of claim 13, i.e. after first execution but before re-execution)).
For claim 15, Vera teaches the limitations of claim 1 for the reasons above and further teaches a data store to which the graphics processing system is configured to write one or more processed outputs in respect of each task of the first type, wherein the graphics processing system is configured to write only one of the first and second processed outputs to the data store (every processor, by definition, has an accumulator and a general purpose register; results of calculation is put in accumulator, and from there to a general purpose register or memory; view these storage locations as said data store).
For claim 18, Vera teaches the limitations of claim 1 for the reasons above and further teaches each processing unit of the plurality of processing units is a different physical core of a graphics processing unit of the graphics processing system (see [0023], [0036]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Vera (US 2009/0113240 A1), and further in view of Williams (US 5,799,022).
Vera teaches the limitations of claim 1
Vera does not explicitly teach the graphics processing system further comprising a check unit operable to form a signature which is characteristic of an output of a processing unit of the plurality of processing units on processing a task, wherein the check unit is configured to form first and second signatures which are characteristic of, respectively, the first and second processed outputs, and wherein the fault detection unit is operable to compare signatures formed at the check unit, the fault detection unit being configured to compare the first and second signatures and raise a fault signal if the first and second signatures do not match (although it is suggested)
However, Williams teaches the graphics processing system further comprising a check unit operable to form a signature which is characteristic of an output of a processing unit of the plurality of processing units on processing a task, wherein the check unit is configured to form first and second signatures which are characteristic of, respectively, the first and second processed outputs, and wherein the fault detection unit is operable to compare signatures formed at the check unit, the fault detection unit being configured to compare the first and second signatures and raise a fault signal if the first and second signatures do not match (see abstract, column2 line 58 through column 3 line 10: signatures are compared for error detection)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Vera to include “the graphics processing system further comprising a check unit … first and second signatures do not match”, as taught by Williams, because each one of Vera and Williams teach comparing processors for error detection therefore they are analogous arts and because comparing the signatures is faster, as they are compressed (see abstract, column2 line 58 through column 3 line 10: signatures are compared for error detection).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIR LEIBOVICH whose telephone number is (571)270-3796. The examiner can normally be reached 8:00am-5:00pm.
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114
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