Prosecution Insights
Last updated: May 29, 2026
Application No. 19/243,979

DISPLAY APPARATUS, ITS OPERATING METHOD, AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Jun 20, 2025
Priority
Aug 12, 2020 — JP 2020-136207 +3 more
Examiner
SARMA, ABHISHEK
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Semiconductor Energy Laboratory Co. Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
483 granted / 577 resolved
+21.7% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
20 currently pending
Career history
596
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
89.6%
+49.6% vs TC avg
§102
4.4%
-35.6% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 577 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the response to this Office Action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 2-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-15 of U.S. Patent 11,984,064 B2. Although the claims at issue are not identical, they are not patentably distinct from each other. The following is an example for comparing claim 1 of this application and claim 10 of U.S. Patent 11,984,064 B2: Claim 1 of this application Claim 10 of U.S. Patent 11,984,064 B2 1. A display apparatus comprising a pixel, the pixel comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; and a light-emitting device, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the light-emitting device, wherein each of the first transistor and the third transistor comprises a first material in a channel formation region, wherein the fourth transistor comprises a second material in a channel formation region, and wherein the first material is different from the second material. 10. A display apparatus comprising a pixel, the pixel comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a capacitor; and a light-emitting device, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor and one of a source and a drain of the fifth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the light-emitting device, wherein each of the first transistor and the third transistor is an n-channel transistor, wherein the fourth transistor is a p-channel transistor, wherein each of the first transistor and the third transistor comprises a first material in a channel formation region, wherein the fourth transistor comprises a second material in a channel formation region, and wherein the first material is different from the second material. The limitations of claim 1 of the current application are broader and are therefore anticipated by those found in claim 10 of U.S. Patent 11,984,064 B2. Claims 2-7 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-15 of U.S. Patent 11,984,064 B2. Although the claims at issue are not identical, they are not patentably distinct from each other. Claims 8-13 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5, and 9 of U.S. Patent 11,984,064 B2. Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 8 recites the additional limitation that the fifth transistor comprises a first material in a channel formation region. Designing the fifth transistor that comprises a first material in a channel formation region would only require only require routine skill for a person of ordinary skill in the art at the time when the invention was filed based on the claims U.S. Patent 11,984,064 B2. In addition, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim 14 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2016/0133190 A1 to Kim et al. (hereinafter "Kim"). Regarding Claim 14, Kim teaches a display apparatus comprising a pixel, the pixel comprising: a first transistor (Fig. 1; Para. 50-60 of Kim; pixel 1 of an organic light emitting diode display… T7); and a light-emitting device electrically connected to the first transistor (Fig. 1; Para. 50-60 of Kim; organic light emitting diode OLED). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-6 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of over U.S. Patent Application Publication 2010/0207920 A1 to Chaji et al. (hereinafter "Chaji"). Regarding Claim 2, Kim teaches a display apparatus comprising a pixel, the pixel comprising: a first transistor (Fig. 1; Para. 50-60 of Kim; pixel 1 of an organic light emitting diode display… T2); a second transistor (Fig. 1; Para. 50-60 of Kim; T3); a third transistor (Fig. 1; Para. 50-60 of Kim; T4); a fourth transistor (Fig. 1; Para. 50-60 of Kim; T7); a fifth transistor (Fig. 1; Para. 50-60 of Kim; T5); a capacitor (Fig. 1; Para. 50-60 of Kim; Cst,); and a light-emitting device (Fig. 1; Para. 50-60 of Kim; organic light emitting diode OLED), wherein each of the first transistor and the third transistor comprises a first material in a channel formation region, wherein the fourth transistor comprises a second material in a channel formation region (Para. 75 of Kim; oxide semiconductor may include one of oxides from among titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), and indium (In)). Kim does not explicitly disclose that one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor, wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the light-emitting device, and wherein the first material is different from the second material. However, Chaji teaches that one of a source and a drain of a first transistor (Fig. 15A; Para. 127-128 of Chaji; T2, transistor 358) is electrically connected to one of a source and a drain of a second transistor and one electrode of a capacitor (Fig. 15A; Para. 127-128 of Chaji; T5, transistor 364.. storage capacitor 344), wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor (Fig. 15A; Para. 127-128 of Chaji; T4, transistor 362) and a gate of a fourth transistor (Fig. 15A; Para. 127-128 of Chaji; T1, transistor 346), wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor (Fig. 15A; Para. 127-128 of Chaji; T1, transistor 346.. storage capacitor 344), wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the light-emitting device (Fig. 15A; Para. 127-128 of Chaji; T6, transistor 366… OLED 342), and wherein a first material is different from a second material (Para. 60, 177 of Chaji; display system that may be fabricated using different fabrication technologies including, for example, but not limited to, amorphous silicon, poly silicon, metal oxide, conventional CMOS, organic, anon/micro crystalline semiconductors or combinations thereof…The transistor may be implemented in a variety of materials systems technologies including, amorphous Si, micro/nano-crystalline Si, poly-crystalline Si, organic/polymer materials and related nanocomposites, semiconducting oxides or combinations thereof… Designing the first material to be different from the second material would only require routine skill for a person of ordinary skill in the art at the time when the invention was filed based on the teachings of Chaji. Therefore, one of ordinary skill in the art would have pursued having the first material to be different from the second material with a reasonable expectation of success that would have yielded predictable results and can be accomplished without any undue experimentation in order to better manage the power requirements of a display apparatus. In addition, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416). Therefore, at the time when the invention was filed, it would have been obvious to a person of ordinary skill in the art to include that that one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor, wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the light-emitting device, and wherein the first material is different from the second material using the teachings of Chaji in order to modify the display apparatus taught by Kim. The motivation to combine these analogous arts would have been to provide a display system and its operation method that can improve the lifetime, image uniformity, stability and/or yield of the display, and can provide a high-resolution stable low power display (Para. 4 of Chaji). Regarding Claim 8, Kim teaches a display apparatus comprising a pixel, the pixel comprising: a first transistor (Fig. 1; Para. 50-60 of Kim; pixel 1 of an organic light emitting diode display… T2); a second transistor (Fig. 1; Para. 50-60 of Kim; T3); a third transistor (Fig. 1; Para. 50-60 of Kim; T4); a fourth transistor (Fig. 1; Para. 50-60 of Kim; T7); a fifth transistor (Fig. 1; Para. 50-60 of Kim; T5); a capacitor (Fig. 1; Para. 50-60 of Kim; Cst,); and a light-emitting device (Fig. 1; Para. 50-60 of Kim; organic light emitting diode OLED), wherein each of the first transistor, the third transistor, and the fifth transistor comprises a first material in a channel formation region, wherein the fourth transistor comprises a second material in a channel formation region (Para. 75 of Kim; oxide semiconductor may include one of oxides from among titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), and indium (In)). Kim does not explicitly disclose that one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor, wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the light-emitting device, and wherein the first material is different from the second material. However, Chaji teaches that one of a source and a drain of a first transistor (Fig. 15A; Para. 127-128 of Chaji; T2, transistor 358) is electrically connected to one of a source and a drain of a second transistor and one electrode of a capacitor (Fig. 15A; Para. 127-128 of Chaji; T5, transistor 364.. storage capacitor 344), wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor (Fig. 15A; Para. 127-128 of Chaji; T4, transistor 362) and a gate of a fourth transistor (Fig. 15A; Para. 127-128 of Chaji; T1, transistor 346), wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor (Fig. 15A; Para. 127-128 of Chaji; T1, transistor 346.. storage capacitor 344), wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the light-emitting device (Fig. 15A; Para. 127-128 of Chaji; T6, transistor 366… OLED 342), and wherein a first material is different from a second material (Para. 60, 177 of Chaji; display system that may be fabricated using different fabrication technologies including, for example, but not limited to, amorphous silicon, poly silicon, metal oxide, conventional CMOS, organic, anon/micro crystalline semiconductors or combinations thereof…The transistor may be implemented in a variety of materials systems technologies including, amorphous Si, micro/nano-crystalline Si, poly-crystalline Si, organic/polymer materials and related nanocomposites, semiconducting oxides or combinations thereof… Designing the first material to be different from the second material would only require routine skill for a person of ordinary skill in the art at the time when the invention was filed based on the teachings of Chaji. Therefore, one of ordinary skill in the art would have pursued having the first material to be different from the second material with a reasonable expectation of success that would have yielded predictable results and can be accomplished without any undue experimentation in order to better manage the power requirements of a display apparatus. In addition, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416). Therefore, at the time when the invention was filed, it would have been obvious to a person of ordinary skill in the art to include that that one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the capacitor, wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the light-emitting device, and wherein the first material is different from the second material using the teachings of Chaji in order to modify the display apparatus taught by Kim. The motivation to combine these analogous arts would have been to provide a display system and its operation method that can improve the lifetime, image uniformity, stability and/or yield of the display, and can provide a high-resolution stable low power display (Para. 4 of Chaji). Regarding Claims 3 and 9, the combination of Kim and Chaji teaches that each of the first transistor and the third transistor is an n-channel transistor, and wherein the fourth transistor, is a p-channel transistor (Fig. 15A; Para. 127-128 of Chaji; transistors 346, 358, 360, 362, 364, and 366 are p-type TFT transistors… Designing the first transistor and the third transistor as an n-channel transistor and the fourth transistor as a p-channel transistor would only require routine skill for a person of ordinary skill in the art based on the combination of Kim and Chaji. Therefore, one of ordinary skill in the art would have pursued having the first transistor and the third transistor as an n-channel transistor and the fourth transistor as a p-channel transistor with a reasonable expectation of success that would have yielded predictable results and can be accomplished without any undue experimentation in order to better manage the power requirements of a display apparatus. In addition, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416). Regarding Claims 4 and 10, the combination of Kim and Chaji teaches that the second transistor is a p-channel transistor (Fig. 15A; Para. 127-128 of Chaji; transistors 346, 358, 360, 362, 364, and 366 are p-type TFT transistors). Regarding Claims 5 and 11, the combination of Kim and Chaji teaches that the first material comprises a metal oxide, wherein the metal oxide comprises indium, and wherein the second material comprises silicon (Para. 75 of Kim; oxide semiconductor may include one of oxides from among titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), and indium (In)… Para. 60, 177 of Chaji; display system that may be fabricated using different fabrication technologies including, for example, but not limited to, amorphous silicon, poly silicon, metal oxide, conventional CMOS, organic, anon/micro crystalline semiconductors or combinations thereof…The transistor may be implemented in a variety of materials systems technologies including, amorphous Si, micro/nano-crystalline Si, poly-crystalline Si, organic/polymer materials and related nanocomposites, semiconducting oxides or combinations thereof). Regarding Claims 6 and 12, the combination of Kim and Chaji teaches that the light-emitting device comprises an organic EL element or a micro LED (Fig. 15A; Para. 127 of Chaji; OLED 342). Allowable Subject Matter Claims 7 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the references, either singularly or in combination, teach or fairly suggest the display apparatus according to according to claim 1, wherein each of the first transistor and the third transistor comprises a back gate, wherein the gate of the first transistor is electrically connected to the back gate of the first transistor, and wherein the gate of the third transistor is electrically connected to the back gate of the third transistor. None of the references, either singularly or in combination, teach or fairly suggest the display apparatus according to according to claim 8, wherein each of the first transistor and the third transistor comprises a back gate, wherein the gate of the first transistor is electrically connected to the back gate of the first transistor, and wherein the gate of the third transistor is electrically connected to the back gate of the third transistor. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABHISHEK SARMA whose telephone number is (571)272-9887. The examiner can normally be reached on Mon - Fri 8:00-5:00. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABHISHEK SARMA/ Primary Examiner, Art Unit 2621
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Prosecution Timeline

Jun 20, 2025
Application Filed
Apr 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
85%
With Interview (+1.6%)
2y 1m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 577 resolved cases by this examiner. Grant probability derived from career allowance rate.

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