DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is made in response to applicant’s amendment submitted on 06/25/2026. No claim has been amended. No claim has been cancelled. No claim has been newly added. Claims 1-20 are currently pending in the application.
Response to Argument
Applicant’s arguments filed on 06/25/2026 have been fully considered but they are not persuasive.
Applicant submits “Applicant submits that Liu describes VGL as a "second power supply line VGL [which] may provide a low-level second power supply signal continuously." Liu, [0167], which is different from being a "voltage control signal" as recited in claim 1. The VGL of Liu is a supply voltage, not a control voltage. Indeed, the Office Action even asserts, in the earlier mapping of Liu with respect to the claimed "sixth transistor" of claim 1, that the VGL of Liu is a "second supply voltage," rather than a "voltage control signal." See Office Action, p. 3, and Liu, 1 [0163].”; and “Liu thus fails to disclose "a ninth transistor comprising a control electrode which receives the voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node," as recited in claim 1. (emphasis added).” (Remarks, page 14, the first paragraph)
Examiner respectfully disagrees with Applicant’s premises and conclusions. Claim states a ninth transistor comprising a control electrode which receives the voltage control signal. Liu discloses a ninth transistor T62 comprising a control electrode (gate electrode) which receives the voltage control signal VGL. Applicant argues that VGL is a second supply voltage rather than a voltage control signal. However, the currently pending claim doesn’t state supply voltage cannot be the same as or function as voltage control signal. As above, if Applicant believes that the current invention is different from Examiner’s interpretation of the prior art regarding the voltage control signal, the claim language should be amended to reflect the difference and more clearly define Applicant’s invention. However, based on the currently pending claim language, Examiner maintains the rejections of the independent claims 1, 9 and 17.
Applicant further submits “Second, with respect to "the output circuit outputs one of the first power supply voltage and a third power supply voltage as the gate signal" recited in claim 1, the Office Action again relies on the second power supply line VGL in Liu, asserting that "the output circuit 12 outputs one of first power supply voltage VGH and third power supply voltage VGL as OUT2 (gate signal)]." Office Action, p. 4.”; “Liu, however, only discloses two power supply lines VGH and VGL for the circuit of FIG. 6. See Liu, FIG. 6, " [0161], [0163], [0167], and [0377]. At best, the second output circuit 12 of Liu outputs one of the first power supply line VGH (already asserted by the Office Action as a "first power supply voltage") or the second power supply line VGL (already asserted by the Office Action as a "voltage control signal" and a "second supply voltage").”; and “Liu thus fails to disclose "the output circuit outputs one of the first power supply voltage and a third power supply voltage as the gate signal," as recited in claim 1. (emphasis added).” (Remarks, page 14, the first paragraph)
Examiner respectfully disagrees with Applicant’s premises and conclusions. Applicant argues that VGL is a second supply voltage rather than a third supply voltage. Again, the currently pending claim doesn’t state a third supply voltage is different from the second supply voltage. As above, if Applicant believes that the current invention is different from Examiner’s interpretation of the prior art regarding the third supply voltage, the claim language should be amended to reflect the difference and more clearly define Applicant’s invention. However, based on the currently pending claim language, Examiner maintains the rejections of the independent claims 1, 9 and 17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US. Pub. No. 2024/0282266, hereinafter “Liu”).
As to claim 1, (Original) Liu discloses a gate driver [figures 6 and 32, a gate driver circuit, paragraph 375] comprising:
an input circuit [figure 6, input circuit T51 which transmits an input signal INPUT to a control circuit T58-T60, T62 and 11 based on first clock signal CK] which transmits an input signal to a control circuit based on a first clock signal;
the control circuit which controls a voltage of a control node based on the input signal,
the first clock signal, a second clock signal, and a voltage control signal [figure 6, the control circuit which controls a voltage of a control node (node between T59 and T60 and connected to OUT1) based on input signal INPUT, first clock signal CK, second clock signal CB and a voltage control signal VGL]; and
an output circuit which outputs a gate signal based on the voltage of the control node [figure 6, an output circuit 12 outputs a gate signal OUT2 based on the voltage of the control node OUT1],
wherein the control circuit comprises:
a fifth transistor [figure 6, transistor T59 comprising a gate electrode connected to node N10, first electrode which receives first power supply voltage VGH, and second electrode connected to the control node] comprising a control electrode connected to a second node, a first electrode which receives a first power supply voltage, and a second electrode connected to the
control node;
a sixth transistor [figure 6, transistor T60 comprising a gate electrode connected to node N9, first electrode connected to the control node, and second electrode which receives a second supply voltage VGL] comprising a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode which receives a second power supply voltage; and
a ninth transistor [figure 6, transistor T62 comprising a gate electrode which receives the voltage control signal VGL, first electrode connected to node N11, second electrode connected to node N9] comprising a control electrode which receives the voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node,
wherein:
the control circuit transmits one of the first power supply voltage and the second power supply voltage to the control node [figure 6, the control circuit 11 transmits one of first power supply voltage VGH and second power supply voltage VGL to the control node], and
the output circuit outputs one of the first power supply voltage and a third power supply voltage as the gate signal [figure 6, the output circuit 12 outputs one of first power supply voltage VGH and third power supply voltage VGL as OUT2 (gate signal)].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Murakami et al. (US. Pub. No. 2014/0098017, hereinafter “Murakami”).
As to claim 9, (Original) Liu discloses a display device [figure 47, display apparatus 91] comprising:
a display panel comprising pixels [paragraph 95, The display region at least includes multiple pixel circuits regularly arranged, multiple gate lines (including, for example, a scan line, a reset control line, and a light emitting control line) extending along a first direction, multiple data lines and power supply lines extending along a second direction];
a gate driver [figure 32, gate driver outputs gate signal to the pixels, paragraph 96, the non-display region is provided with a gate driver circuit, the gate driver circuit includes multiple cascaded drive control circuits, and a drive control circuit may be configured to provide a gate drive signal to a pixel circuit of the display region] which outputs a gate signal to the pixels; and
wherein the gate driver comprises:
an input circuit [figure 6, input circuit T51 which transmits an input signal INPUT to a control circuit T58-T60, T62 and 11 based on first clock signal CK] which transmits an input signal to a control circuit based on a first clock signal;
the control circuit which controls a voltage of a control node based on the input signal,
the first clock signal, a second clock signal, and a voltage control signal [figure 6, the control circuit which controls a voltage of a control node (node between T59 and T60 and connected to OUT1) based on input signal INPUT, first clock signal CK, second clock signal CB and a voltage control signal VGL]; and
an output circuit which outputs the gate signal based on the voltage of the control node [figure 6, an output circuit 12 outputs a gate signal OUT2 based on the voltage of the control node OUT1],
wherein the control circuit comprises:
a fifth transistor [figure 6, transistor T59 comprising a gate electrode connected to node N10, first electrode which receives first power supply voltage VGH, and second electrode connected to the control node] comprising a control electrode connected to a second node, a first
electrode which receives a first power supply voltage, and a second electrode connected to the
control node;
a sixth transistor [figure 6, transistor T60 comprising a gate electrode connected to node N9, first electrode connected to the control node, and second electrode which receives a second supply voltage VGL] comprising a control electrode connected to a fourth node, a first
electrode connected to the control node, and a second electrode which receives a second power supply voltage; and
a ninth transistor [figure 6, transistor T62 comprising a gate electrode which receives the voltage control signal VGL, first electrode connected to node N11, second electrode connected to node N9] comprising a control electrode which receives the voltage control
signal, a first electrode connected to a third node, and a second electrode connected to the
fourth node,
wherein:
the control circuit transmits one of the first power supply voltage and the second power supply voltage to the control node [figure 6, the control circuit 11 transmits one of first power supply voltage VGH and second power supply voltage VGL to the control node], and
the output circuit outputs one of the first power supply voltage and a third power supply voltage as the gate signal [figure 6, the output circuit 12 outputs one of first power supply voltage VGH and third power supply voltage VGL as OUT2 (gate signal)].
Liu does not expressly disclose a data driver which outputs a data voltage to the pixels.
Murakami teaches a display device comprising a data driver which outputs a data voltage to pixels [figure 1, display device 1 comprising a data driver 300 which outputs a data voltage SL to pixels].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Liu to comprise a data driver which outputs a data voltage to the pixels, as taught by Murakami, in order to supply a source signal to each data signal line (Murakami, paragraph 83).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Huang et al. (US. Pub. No. 2020/0387282, hereinafter “Huang”).
As to claim 17, (Original) Liu discloses an electronic device [figure 47, electronic device 91] comprising:
a display panel comprising pixels [paragraph 95, The display region at least includes multiple pixel circuits regularly arranged, multiple gate lines (including, for example, a scan line, a reset control line, and a light emitting control line) extending along a first direction, multiple data lines and power supply lines extending along a second direction];
a gate driver [figure 32, gate driver outputs gate signal to the pixels, paragraph 96, the non-display region is provided with a gate driver circuit, the gate driver circuit includes multiple cascaded drive control circuits, and a drive control circuit may be configured to provide a gate drive signal to a pixel circuit of the display region] which outputs a gate signal to the pixels;
wherein the gate driver comprises:
an input circuit [figure 6, input circuit T51 which transmits an input signal INPUT to a control circuit T58-T60, T62 and 11 based on first clock signal CK] which transmits an input signal to a control circuit based on a first clock signal;
the control circuit which controls a voltage of a control node based on the input signal,
the first clock signal, a second clock signal, and a voltage control signal [figure 6, the control circuit which controls a voltage of a control node (node between T59 and T60 and connected to OUT1) based on input signal INPUT, first clock signal CK, second clock signal CB and a voltage control signal VGL]; and
an output circuit which outputs the gate signal based on the voltage of the control node [figure 6, an output circuit 12 outputs a gate signal OUT2 based on the voltage of the control node OUT1],
wherein the control circuit comprises:
a fifth transistor [figure 6, transistor T59 comprising a gate electrode connected to node N10, first electrode which receives first power supply voltage VGH, and second electrode connected to the control node] comprising a control electrode connected to a second node, a first electrode which receives a first power supply voltage, and a second electrode connected to the control node;
a sixth transistor [figure 6, transistor T60 comprising a gate electrode connected to node N9, first electrode connected to the control node, and second electrode which receives a second supply voltage VGL] comprising a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode which receives a second power supply voltage; and
a ninth transistor [figure 6, transistor T62 comprising a gate electrode which receives the voltage control signal VGL, first electrode connected to node N11, second electrode connected to node N9] comprising a control electrode which receives the voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node,
wherein:
the control circuit transmits one of the first power supply voltage and the second power supply voltage to the control node [figure 6, the control circuit 11 transmits one of first power supply voltage VGH and second power supply voltage VGL to the control node], and
the output circuit outputs one of the first power supply voltage and a third power supply voltage as the gate signal [figure 6, the output circuit 12 outputs one of first power supply voltage VGH and third power supply voltage VGL as OUT2 (gate signal)].
Liu does not expressly disclose a processor which outputs an input control signal and input image data;
a data driver which outputs a data voltage to the pixels; and
a driving controller which controls the gate driver and the data driver based on the
input control signal and the input image data.
Huang teaches an electronic device comprising a processor which outputs an input control signal and input image data [figure 5, electronic device 300 comprising timing controller 320 (using one or more microprocessors per paragraph 80) which outputs input control signal CONT1, CONT2 and input image data RGBD];
a data driver [figure 5, data driver 340 outputs data voltage to pixels, paragraph 82, The data driver 340 receives the second control signal CONT2 and the output image data RGBD′ from the timing sequence controller 320. The data driver 340 generates a plurality of data voltages based on the second control signal CONT2 and the output image data RGBD′. The data driver 340 may apply the generated plurality of data voltages to the data lines DL] which outputs a data voltage to the pixels; and
a driving controller which controls the gate driver and the data driver based on the
input control signal and the input image data [figure 5, timing controller 320 controls gate driver 330 and data driver 340 based on the input control signal CONT1 and CONT2 and image data RGBD].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Liu to comprise a processor which outputs an input control signal and input image data; a data driver which outputs a data voltage to the pixels; and a driving controller which controls the gate driver and the data driver based on the input control signal and the input image data, as taught by Huang, since it is applying a known technique to a known display device ready for improvement to yield predictable results.
Allowable Subject Matter
Claims 2-8, 10-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combination limitations of dependent claims 2, 10 and 18, such as “the input circuit comprises a first transistor comprising a control electrode which receives the first clock signal, a first electrode which receives the input signal, and a second electrode connected to a first node, and the control circuit further comprises: a second transistor comprising a control electrode which receives the third power supply voltage, a first electrode connected to the first node, and a second electrode connected to the third node; a third transistor comprising a control electrode connected to the third node, a first electrode which receives the second clock signal, and a second electrode connected to the second node; a fourth transistor comprising a control electrode which receives the first clock signal, a first electrode which receives the first power supply voltage, and a second electrode connected to the second node; a first capacitor comprising a first electrode connected to the second node and a second electrode connected to the third node; a second capacitor comprising a first electrode which receives the first power supply voltage and a second electrode connected to the second node; and a third capacitor comprising a first electrode connected to the second node and a second electrode connected to the fourth node”, recited by claims 2, 10 and 18, respectively.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN LEE can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NAN-YING YANG/Primary Examiner, Art Unit 2629
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