DETAILED ACTION
This is a first office action in response to Application No. 19/244,014 originally filed on 06/20/2025, in which claims 1 - 20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1 - 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang “US 2023/0109049” in view of Park “US 2018/0226028”.
Re-claim 1, Wang teaches a display device (par. [0006] a stretchable display panel and a display device) comprising:
a substrate (fig. 3; 111) in which a plurality of island portions (fig. 3; 11) and a plurality of bridge portions (fig. 3; 12) connecting the plurality of island portions (fig. 3; 11) are defined;
each of the plurality of island portions (fig. 3; 11)
the plurality of island portions (fig. 3; 11)
Wang does not explicitly teach first pixel circuit arranged … in and connected to a first data line; and
a light-emitting element arranged in each of … and connected to the first pixel circuit,
wherein the first pixel circuit comprises:
a first transistor connected between a first driving voltage line and the light- emitting element and configured to control a current supplied to the light-emitting element;
a first capacitor connected between:
a first node connected to a gate of the first transistor, and
an initialization voltage line;
a second transistor connected between the first node and a second node and comprising a gate connected to a first gate line;
a second capacitor connected between the first data line and the second node; and
a third transistor connected between the second node and a third node connected to the light-emitting element, wherein the third transistor comprises a gate connected to a second gate line.
However, Park teaches a first pixel circuit (fig. 8) arranged … in and connected to a first data line; (fig. 8; D(j)) and
a light-emitting element (fig. 8; OLED) arranged in each of … and connected to the first pixel circuit, (fig. 8)
wherein the first pixel circuit (fig. 8) comprises:
a first transistor (fig. 8; T1) connected between a first driving voltage line (fig. 8; ELVDD) and the light- emitting element (fig. 8; OLED) and configured to control a current supplied to the light-emitting element (fig. 8; OLED); (par. [0084] The OLED may emit light based on driving current flowing from the first transistor T1.)
a first capacitor (fig. 8; Cst) connected between:
a first node (fig. 8; N1) connected to a gate of the first transistor, (fig. 8; T1) and
an initialization voltage line; (fig. 8; VINT)
a second transistor (fig. 8; T2) connected between the first node (fig. 8; N1) and a second node (fig. 8; N3) and comprising a gate connected to a first gate line; (fig. 8; S(i))
a second capacitor (fig. 8; Cpr) connected between the first data line (fig. 8; D(j)) and the second node; (fig. 8; N3) and
a third transistor (fig. 8; T3) connected between the second node (fig. 8; N3) and a third node (fig. 8; N2) connected to the light-emitting element, (fig. 8; OLED) wherein the third transistor (fig. 8; T3) comprises a gate connected to a second gate line. (fig. 8; S(i+1))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang into Park, since the claimed elements were known in the prior art and a stretchable display device as disclosed by Wang with a pixel circuit of Park, and since this just a simple substitution known element for another to obtain predictable results.
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Re-claim 2, Wang in view of Park teaches all the limitations of claim 1, Park teaches wherein: the first capacitor (fig. 8; Cst) comprises a first capacitor electrode and a second capacitor electrode arranged on the first capacitor electrode, (fig. 8) and
the first capacitor electrode (fig. 8; Cst) is a part of the gate of the first transistor. (fig. 8; T1)
Re-claim 3, Wang in view of Park teaches all the limitations of claim 2, Park teaches wherein: the second capacitor (fig. 8; Cpr) comprises a third capacitor electrode and a fourth capacitor electrode arranged on the third capacitor electrode, (fig. 8) and
the third capacitor electrode is arranged on a same layer as the gate of the first transistor. (fig. 8 and pars. [0071] and [0076])
Re-claim 4, Wang in view of Park teaches all the limitations of claim 3, Wang teaches wherein a first insulating layer is arranged between the first capacitor electrode and the second capacitor electrode and between the third capacitor electrode and the fourth capacitor electrode. (fig. 6 and par. [0084] which is a schematic view of a laminated structure of film layers of the display panel … an area where the island structure 11)
Re-claim 20, is rejected as applied to claim 1 above because the scope and contents of the recited limitations are substantially the same.
7. Claims 5 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Wang “US 2023/0109049” in view of Park “US 2018/0226028” and further in view of Son “US 2023/0029234”.
Re-claim 5, Wang in view of Park teaches all the limitations of claim 2 but do not explicitly teach wherein: the first pixel circuit further comprises a third capacitor connected between the third node and the initialization voltage line, and
the third capacitor comprises a fifth capacitor electrode and a sixth capacitor electrode on the fifth capacitor electrode.
However, Son teaches wherein: the first pixel circuit (fig. 20) further comprises a third capacitor (fig. 20; C52) connected between the third node (fig. 20; n3) and the initialization voltage line, (fig. 20 and par. [0191] In the sensing step Ts, as shown in FIG. 21, when the voltage DTS at the third node n3 rise and thus the voltage between the second and third nodes n2 and n3, that is, the gate-source voltage Vgs of the driving element DT reaches a threshold voltage Vth, the driving element DT is turned off and the threshold voltage is stored in the capacitor Cst.) and
the third capacitor (fig. 20; C52) comprises a fifth capacitor electrode and a sixth capacitor electrode on the fifth capacitor electrode. (fig. 20)
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Wang into Park with the teaching of Son, the claimed elements were known in the prior art and a pixel circuit as disclosed by Son, since just a simple substitution known element for another to obtain predictable results.
Re-claim 6, Wang, Park in view of Son teaches all the limitations of claim 5, Son teaches wherein the sixth capacitor electrode is formed integrally with the second capacitor electrode. (fig. 20)
Allowable Subject Matter
8. Claims 7 - 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sosina Abebe whose telephone number is (571) 270-7929. The examiner can normally be reached on Mon-Friday from 9:00-5:30 If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, Temesghen Ghebretinsae can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/S.A/Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 2/27/26C