DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,375,067. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application and the claims of the patent commonly claim, as follows:
19/245,453
12,375,067
1.
A circuit for adjusting a periodic input signal, comprising:
a duty cycle calibration (DCC) device, configured to generate a first signal and a
second signal in response to the periodic input signal;
a phase adjusting device, configured to receive the first signal and the second signal
and generate a third signal by combining the first signal and the second signal based on a
selection signal; and
a duty cycle measurement (DCM) device, configured to measure and adjust a duty
cycle of the third signal so that the selection signal is adjusted to generate a periodic output signal, wherein a frequency of the periodic output signal is twice that of the periodic input signal.
1.
A circuit for adjusting a periodic input signal, comprising:
a duty cycle calibration device, configured to generate a first signal and a second
signal in response to the periodic input signal, wherein the first signal and the second signal have different phases;
a phase adjusting device, configured to receive the first signal and the second signal
and generate a third signal by combining the first signal and the second signal based on a
selection signal; and
a duty cycle measurement (DCM) device, configured to measure and adjust a duty
cycle of the third signal so that the selection signal is adjusted to generate a periodic output signal, wherein a frequency of the periodic output signal is twice that of the periodic input signal.
2.
The circuit of Claim 1, wherein a first portion of the first signal is extracted to obtain the third signal when the selection signal is on a low logic value, and a second portion of the second signal is extracted to obtain the third signal when the selection signal is on a high logic value.
2.
The circuit of Claim 1, wherein a first portion of the first signal is extracted to obtain the third signal when the selection signal is on a low logic value, and a second portion of the second signal is extracted to obtain the third signal when the selection signal is on a high logic value.
3.
The circuit of Claim 1, wherein the first signal is at a high logic value while the second signal is at a low logic value, and the first signal is at a low logic value while the second signal is at a high logic value.
4.
The circuit of Claim 1, wherein the DCM device is configured to generate a fourth signal and a fifth signal in accordance with the duty cycle of the third signal, wherein the fourth signal indicates half of a period of the third signal, and the fifth signal indicates a duration in which the third signal is at a high logic value.
3.
The circuit of Claim 1, wherein the first signal is at a high logic value while the second signal is at a low logic value, and the first signal is at a low logic value while the second signal is at a high logic value.
4.
The circuit of Claim 1, wherein the DCM device is configured to generate a fourth signal and a fifth signal in accordance with the duty cycle of the third signal, wherein the fourth signal indicates half of a period of the third signal, and the fifth signal indicates a duration in which the third signal is at a high logic value.
5.
The circuit of Claim 4, wherein if the fourth signal is greater than the fifth signal in amplitude, the selection signal is delayed by the phase adjusting device and the DCM device to increase the duty cycle of the third signal.
5.
The circuit of Claim 4, wherein if the fourth signal is greater than the fifth signal in amplitude, the selection signal is delayed by the phase adjusting device and the DCM device to increase the duty cycle of the third signal.
6.
The circuit of Claim 4, wherein if the fourth signal is smaller than the fifth signal in amplitude, the selection signal is shifted by the phase adjusting device and the DCM device to decrease the duty cycle of the third signal.
6.
The circuit of Claim 4, wherein if the fourth signal is smaller than the fifth signal in amplitude, the selection signal is shifted by the phase adjusting device and the DCM device to decrease the duty cycle of the third signal.
7.
The circuit of Claim 4, wherein if the fourth signal is substantially equal to the fifth signal in amplitude, the periodic output signal is generated having the duty cycle of substantially 50%.
7.
The circuit of Claim 4, wherein if the fourth signal is substantially equal to the fifth signal in amplitude, the periodic output signal is generated having the duty cycle of substantially 50%.
8.
The circuit of Claim 4, wherein the DCC device is configured to generate a sixth signal indicating a quarter of a period of the periodic input signal.
8.
The circuit of Claim 4, wherein the DCC device is configured to generate a sixth signal indicating a quarter of a period of the periodic input signal.
9.
The circuit of Claim 8, wherein the circuit further comprises a code generator, configured to generate a seventh signal by combining the sixth signal from the
DCC device with the fourth signal and the fifth signal from the DCM device, wherein the
phase adjusting device is configured to adjust the selection signal corresponding to the
seventh signal.
9.
The circuit of Claim 8, wherein the circuit further comprises a code generator, configured to generate a seventh signal by combining the sixth signal from the
DCC device with the fourth signal and the fifth signal from the DCM device, wherein the
phase adjusting device is configured to adjust the selection signal corresponding to the
seventh signal.
10.
The circuit of Claim 9, wherein the phase adjusting device further comprises:
a multiplexer, configured to receive the first signal and the second signal and generate the third signal;
a delay chain, configured to receive the seventh signal from the code generator; and a divider, electrically coupled between the multiplexer and the delay device.
10.
The circuit of Claim 9, wherein the phase adjusting device further comprises:
a multiplexer, configured to receive the first signal and the second signal and
generate the third signal;
a delay chain, configured to receive the seventh signal from the code generator; and
a divider, electrically coupled between the multiplexer and the delay device.
11.
A method for adjusting a periodic input signal, comprising:
generating, by a duty cycle calibration (DCC) device, a first signal and a second
signal in response to the periodic input signal;
generating, by a phase adjusting device, a third signal by combining the first signal
and the second signal based on a selection signal;
measuring, by a duty cycle measurement (DCM) device, a duty cycle of the third
signal; and
adjusting, by the DCM device and the phase adjusting device, the selection signal
based on the duty cycle of the third signal to generate a periodic output signal, wherein a
frequency of the periodic output signal is twice that of the periodic input signal.
11.
A method for adjusting a periodic input signal, comprising:
generating, by a duty cycle calibration (DCC) device, a first signal and a second
signal in response to the periodic input signal, wherein the first signal and the second signal have different phases;
generating, by a phase adjusting device, a third signal by combining the first signal
and the second signal based on a selection signal;
measuring, by a duty cycle measurement (DCM) device, a duty cycle of the third
signal; and
adjusting, by the DCM device and the phase adjusting device, the selection signal
based on the duty cycle of the third signal to generate a periodic output signal, wherein a
frequency of the periodic output signal is twice that of the periodic input signal.
12.
The method of Claim 11, further comprising:
extracting, by the phase adjusting device, a first portion of the first signal to obtain
the third signal when the selection signal is on a low logic value; and
extracting, by the phase adjusting device, a second portion of the second signal to
obtain the third signal when the selection signal is on a high logic value.
12.
The method of Claim 11, further comprising:
extracting, by the phase adjusting device, a first portion of the first signal to obtain
the third signal when the selection signal is on a low logic value; and
extracting, by the phase adjusting device, a second portion of the second signal to
obtain the third signal when the selection signal is on a high logic value.
13.
The method of Claim 11, further comprising generating a fourth signal and a fifth signal based on the duty cycle of the third signal, wherein the fourth signal indicates half of a period of the third signal, and the fifth signal indicates a duration in which the third signal is at a high logic value.
13.
The method of Claim 11, further comprising generating a fourth signal and a fifth signal based on the duty cycle of the third signal, wherein the fourth signal indicates half of a period of the third signal, and the fifth signal indicates a duration in which the third signal is at a high logic value.
14.
The method of Claim 13, further comprising increasing the duty cycle of the third signal by delaying the selection signal if the fourth signal is greater than the fifth signal in amplitude.
14.
The method of Claim 13, further comprising increasing the duty cycle of the third signal by delaying the selection signal if the fourth signal is greater than the fifth signal in amplitude.
15.
The method of Claim 13, further comprising decreasing the duty cycle of the third signal by advancing the selection signal if the fourth signal is smaller than the fifth signal in amplitude.
15.
The method of Claim 13, further comprising decreasing the duty cycle of the third signal by advancing the selection signal if the fourth signal is smaller than the fifth signal in amplitude.
16.
The method of Claim 13, further comprising generating the periodic output signal having the duty cycle of substantially 50% if the fourth signal is substantially equal to the fifth signal.
16.
The method of Claim 13, further comprising generating the periodic output signal having the duty cycle of substantially 50% if the fourth signal is substantially equal to the fifth signal.
17.
The method of Claim 13, further comprising generating a sixth signal representing a quarter of a period of the periodic input signal.
17.
The method of Claim 13, further comprising generating a sixth signal representing a quarter of a period of the periodic input signal.
18.
The method of Claim 17, further comprising:
generating, by a code generator, a seventh signal by combining the sixth signal, the
fourth signal and the fifth signal; and
adjusting, by the phase adjusting device, the selection signal in response to the seventh signal.
18.
The method of Claim 17, further comprising:
generating, by a code generator, a seventh signal by combining the sixth signal, the
fourth signal and the fifth signal; and
adjusting, by the phase adjusting device, the selection signal in response to the seventh signal.
19.
A circuit for adjusting a periodic input signal, comprising:
a phase adjusting device, configured to receive a first signal and a second signal to generate a third signal,
wherein the third signal is generated by synthesizing the first signal and the second signal in accordance with a selection signal; and a duty cycle measurement (DCM) device, configured to develop a feedback loop with the phase adjusting device, wherein:
the DCM device is configured to receive the third signal and generate a fourth signal and a fifth signal based on a duty cycle of the third signal to advance or delay an edge of the third signal, which indicates a transition between a high logic value and a low logic value, until the duty cycle of the third signal is substantially 50%.
19.
A circuit for adjusting a periodic input signal, comprising:
a phase adjusting device, configured to receive a first signal and a second signal to generate a third signal having twice of a frequency of the periodic input signal, wherein the first signal and the second signal are extracted from the periodic input signal, and the third signal is generated by synthesizing the first signal and the second signal in accordance with a selection signal; and a duty cycle measurement (DCM) device, configured to develop a feedback loop with the phase adjusting device, wherein:
the DCM device is configured to receive the third signal and generate a fourth signal and a fifth signal based on a duty cycle of the third signal to advance or delay an edge of the third signal, which indicates a transition between a high logic value and a low logic value, until the duty cycle of the third signal is substantially 50%.
20.
The circuit of Claim 19, wherein the edge of the selection signal is delayed to increase the duty cycle of the third signal if the fourth signal is greater than the fifth signal, and the edge of the selection signal is advanced to decrease the duty cycle of the third signal if the fourth signal is greater than the fifth signal.
20.
The circuit of Claim 19, wherein the edge of the selection signal is delayed to increase the duty cycle of the third signal if the fourth signal is greater than the fifth signal, and the edge of the selection signal is advanced to decrease the duty cycle of the third signal if the fourth signal is greater than the fifth signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ting et al. (US 11,387,813) discloses a duty cycle calibration method. Albel et al. (US 10,911,165) discloses a system and method of calibrating a frequency doubler including duty cycle adjustment and measurement.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays.
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/CASSANDRA F COX/Primary Examiner, Art Unit 2836
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