DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 06/23/2026 has been entered. Claims 1, 14 and 18 have been amended. Claims 1-20 are pending.
Response to Arguments
Applicant's arguments filed on 06/23/2026 have been fully considered but they are not persuasive.
Regarding claim 1, 14 and 18, applicant argues on pages 11-17 of the Remarks that So does not disclose that a display panel driver intentionally controls a selected pixel in a low-grayscale display region to emit with a low grayscale inconsistent with the first high grayscale and the first low grayscale as part of the first display pattern. Therefore, it is respectfully submitted that SO does not disclose "wherein in response to the state in which the display panel emits with the first display pattern, the display panel driver is configured to control at least one pixel of the second display region to emit with a second low grayscale which is inconsistent with the first high grayscale and the first low grayscale,"
In response to the applicant’s argument, examiner respectfully disagrees. SO describes low-grayscale line data in a first period in fig. 15-16 and paragraph 151, “Accordingly, the pixel driving voltage EVDD can gradually increase in the first period P1.” Paragraph 158 describes, “since the pixel driving voltage EVDD can be changed even by the PWM driving of all the second pixel lines, mura can occur on the first display area on which the low-grayscale line data are displayed.” Paragraph 160 describes, “the mura occurrence area on which the mura occurs on the first display area can include a dark stripe area which occurs in the first period P1 and on which the mura is displayed with a luminance that is smaller than a luminance value of the low-grayscale line data” Fig. 1, 24 and Paragraph 197 describes, “the timing controller 130 can receive the measurement value of the pixel driving voltage EVDD from the voltage sensing circuit 160 that measures the pixel driving voltage EVDD output from the power supply circuit 140, and can determine whether the pixel driving voltage EVDD is changed” The grayscale value of the pixel lines in the display region are adjustable based on the status of the EVDD. The claim does not disclose intentional control to emit a low grayscale inconsistent with the first high grayscale and the first low grayscale nor does the specification describes that feature verbatim. SO describes the above limitation. The rejection is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9, 14, and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by So et al. (US Pub. 20250232701).
Regarding Claim 1, SO discloses:
A display device, (at least refer to fig. 1 and paragraph 69. Describes a display device) comprising:
A display panel configured to emit with a first display pattern during a first time period, (at least refer to fig. 6 and paragraphs 131-132. Describes the display panel driver can write pieces of line data that constitute one piece of frame data on the plurality of pixel lines. Here, one piece of frame data corresponds to an image of one frame that is displayed on the display panel 100 in one frame period. Para. 132, describes: the display panel driver can write low-grayscale line data that is the line data having a low luminance value on all over the pixel lines. In this case, a low-grayscale pattern LGP can be displayed on the display area AA of the display panel 100) the display panel including:
A plurality of display regions, (at least refer to fig. 8 and paragraph 137. Describes an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area); and
A display panel driver configured to drive the display panel, (at least refer to fig. 1 and paragraphs 85-86. Describes the display panel driver writes pixel data of an input image in the pixel circuits of the display panel 100 under the control of a timing controller 130. Para. 86, describes: The display panel driver includes a data driving circuit 110 and a gate driving circuit 120)
Wherein in response to a state in which the display panel emits with the first display pattern, a first display region emits with a first high grayscale, and a second display region emits with a first low grayscale lower than the first high grayscale, (at least refer to fig. 8 and paragraph 137. Describes a low-grayscale pattern LGP and a high-grayscale pattern HGP can be displayed together. Further, hereinafter, an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area) and
Wherein in response to the state in which the display panel emits with the first display pattern, the display panel driver is configured to control at least one pixel of the second display region to emit with a second low grayscale which is inconsistent with the first high grayscale and the first low grayscale, (at least refer to fig. 1, 15-16, 24 and paragraphs 151, 158, 160, and 197. Describes Accordingly, the pixel driving voltage EVDD can gradually increase in the first period P1. Para. 158, describes: since the pixel driving voltage EVDD can be changed even by the PWM driving of all the second pixel lines, mura can occur on the first display area on which the low-grayscale line data are displayed. Para. 160, describes: the mura occurrence area on which the mura occurs on the first display area can include a dark stripe area which occurs in the first period P1 and on which the mura is displayed with a luminance that is smaller than a luminance value of the low-grayscale line data. Para. 197, describes: the timing controller 130 can receive the measurement value of the pixel driving voltage EVDD from the voltage sensing circuit 160 that measures the pixel driving voltage EVDD output from the power supply circuit 140, and can determine whether the pixel driving voltage EVDD is changed).
Regarding Claim 14, SO discloses:
An electronic device, (at least refer to fig. 1 and paragraph 69. Describes a display device) comprising:
A processor configured to output input image data and an input control signal, (at least refer to fig. 1 and paragraphs 93-94. Describes a display device The timing controller 130 can convert the video data to suit a data format that is used in the data driving circuit 110, and can transmit the converted video data to the data driving circuit 110. Para. 94, describes: The timing controller 130 can generate a data timing control signal for controlling an operation timing of the data driving circuit 110, a gate timing control signal for controlling an operation timing of the gate driving circuit 120);
A display panel configured to emit with a first display pattern during a first time period, (at least refer to fig. 6 and paragraphs 131-132. Describes the display panel driver can write pieces of line data that constitute one piece of frame data on the plurality of pixel lines. Here, one piece of frame data corresponds to an image of one frame that is displayed on the display panel 100 in one frame period. Para. 132, describes: the display panel driver can write low-grayscale line data that is the line data having a low luminance value on all over the pixel lines. In this case, a low-grayscale pattern LGP can be displayed on the display area AA of the display panel 100) the display panel including:
A plurality of display regions, (at least refer to fig. 8 and paragraph 137. Describes an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area); and
A display panel driver configured to drive the display panel based on the input image data and the input control signal, (at least refer to fig. 1 and paragraphs 85, 93-94. Describes the display panel driver writes pixel data of an input image in the pixel circuits of the display panel 100 under the control of a timing controller 130. Para. 93, describes: the timing controller 130 can convert the video data to suit a data format that is used in the data driving circuit 110, and can transmit the converted video data to the data driving circuit 110. Para. 94, describes: The timing controller 130 can generate a data timing control signal for controlling an operation timing of the data driving circuit 110, a gate timing control signal for controlling an operation timing of the gate driving circuit 120)
Wherein in response to the state in which the display panel emits with the first display pattern, a first display region emits with a first high grayscale, and a second display region emits with a first low grayscale lower than the first high grayscale, (at least refer to fig. 8 and paragraph 137. Describes a low-grayscale pattern LGP and a high-grayscale pattern HGP can be displayed together. Further, hereinafter, an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area) and
Wherein in response to the state in which the display panel emits with the first display pattern, the display panel driver is configured to control at least one pixel of the second display region to emit with a second low grayscale which is inconsistent with the first high grayscale and the first low grayscale, (at least refer to fig. 1, 15-16, 24 and paragraphs 151, 158, 160, and 197. Describes Accordingly, the pixel driving voltage EVDD can gradually increase in the first period P1. Para. 158, describes: since the pixel driving voltage EVDD can be changed even by the PWM driving of all the second pixel lines, mura can occur on the first display area on which the low-grayscale line data are displayed. Para. 160, describes: the mura occurrence area on which the mura occurs on the first display area can include a dark stripe area which occurs in the first period P1 and on which the mura is displayed with a luminance that is smaller than a luminance value of the low-grayscale line data. Para. 197, describes: the timing controller 130 can receive the measurement value of the pixel driving voltage EVDD from the voltage sensing circuit 160 that measures the pixel driving voltage EVDD output from the power supply circuit 140, and can determine whether the pixel driving voltage EVDD is changed).
Regarding Claim 18, SO discloses:
A display device, (at least refer to fig. 1 and paragraph 69. Describes a display device) comprising:
A display panel configured to emit with a first display pattern during a first time period, (at least refer to fig. 6 and paragraphs 131-132. Describes the display panel driver can write pieces of line data that constitute one piece of frame data on the plurality of pixel lines. Here, one piece of frame data corresponds to an image of one frame that is displayed on the display panel 100 in one frame period. Para. 132, describes: the display panel driver can write low-grayscale line data that is the line data having a low luminance value on all over the pixel lines. In this case, a low-grayscale pattern LGP can be displayed on the display area AA of the display panel 100) the display panel including:
A plurality of display regions, (at least refer to fig. 8 and paragraph 137. Describes an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area); and
A display panel driver configured to drive the display panel, (at least refer to fig. 1 and paragraphs 85-86. Describes the display panel driver writes pixel data of an input image in the pixel circuits of the display panel 100 under the control of a timing controller 130. Para. 86, describes: The display panel driver includes a data driving circuit 110 and a gate driving circuit 120)
Wherein in response to a state in which the display panel emits with the first display pattern, a first data voltage is applied to a first display region, and a second data voltage which is inconsistent with the first data voltage is applied to a second display region, (at least refer to fig. 5, 8 and paragraphs 137, 132. Describes a low-grayscale pattern LGP and a high-grayscale pattern HGP can be displayed together. Here, the high grayscale can mean a grayscale that is larger than 63 G. Further, hereinafter, an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area. Para. 132, describes: the grayscale value and the luminance value can be in proportion to each other, and a low grayscale can mean a grayscale that is equal to or smaller than 63 G in a gamma curve on which the maximum grayscale is 255 G. Fig. 5 depicts data voltage value in correspondence to the grayscale value) and
Wherein in response to the state in which the display panel emits with the first display pattern, the display panel driver is configured to apply a third data voltage which is inconsistent with the first data voltage and the second data voltage to at least one pixel included in the second display region, (at least refer to fig. 1, 15-16, 24, 27 and paragraphs 151, 158, 160, 197 and 216. Describes Accordingly, the pixel driving voltage EVDD can gradually increase in the first period P1. Para. 158, describes: since the pixel driving voltage EVDD can be changed even by the PWM driving of all the second pixel lines, mura can occur on the first display area on which the low-grayscale line data are displayed. Para. 160, describes: the mura occurrence area on which the mura occurs on the first display area can include a dark stripe area which occurs in the first period P1 and on which the mura is displayed with a luminance that is smaller than a luminance value of the low-grayscale line data. Para. 197, describes: the timing controller 130 can receive the measurement value of the pixel driving voltage EVDD from the voltage sensing circuit 160 that measures the pixel driving voltage EVDD output from the power supply circuit 140, and can determine whether the pixel driving voltage EVDD is changed. Para. 216, describes: the mura can be compensated for by decreasing the reference voltage Vref in the first period T1 in which the pixel driving voltage EVDD increases in the PWM interval of the second pixel line).
Regarding Claim 9, SO discloses:
Wherein the second display region includes a plurality of pixel groups, wherein each of the plurality of pixel groups includes a plurality of pixels, and wherein in response to the state in which the display panel emits with the first display pattern, at least one pixel of the plurality of pixels emit with the second tow grayscale, (at least refer to fig. 15-16, 24 and paragraphs 151, 158, and 160. Describes Accordingly, the pixel driving voltage EVDD can gradually increase in the first period P1. Para. 158, describes: since the pixel driving voltage EVDD can be changed even by the PWM driving of all the second pixel lines, mura can occur on the first display area on which the low-grayscale line data are displayed. Para. 160, describes: the mura occurrence area on which the mura occurs on the first display area can include a dark stripe area which occurs in the first period P1 and on which the mura is displayed with a luminance that is smaller than a luminance value of the low-grayscale line data).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 15-16, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over So et al. (US Pub. 20250232701) in view of Inada (US Pub. 20130021390).
Regarding Claim 19, SO does not disclose:
Wherein the first display pattern is a mosaic pattern which is a first sub-pattern displaying white and a second sub-pattern displaying black are alternatively disposed.
Inada teach:
Wherein the first display pattern is a mosaic pattern which is a first sub-pattern displaying white and a second sub-pattern displaying black are alternatively disposed, (at least refer to fig. 5, 7 and paragraph 119-120. Describes the output tone of pixel data that is written to the first region during the first display period is 186, and the output tone of pixel data that is written to the second region during the first display period is 255. Para. 120, describes: the output tone of pixel data that is written to the first region is low during the first display period. For this reason, assuming the luminance of the backlight 2 as 100%, the first region appears to be dark and grayish during the first display period. This causes the pattern that is displayed on the liquid crystal panel 1 during the first display period to be a white-and-gray checkered pattern).
The two references are analogous art because they are related with the same field of invention of display device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate checkered pattern display as taught by Inada with the display device as disclose by SO. The motivation to combine the reference of Inada is to protect privacy and improve the display quality of an image by utilizing a phenomenon of a checkered pattern appearing when the panel is looked at obliquely and making it hard to see characters that are displayed in the first region when the panel is looked at squarely.
Regarding Claim 2, SO does not disclose:
Wherein the first display pattern is a mosaic pattern which is a first sub-pattern emitting as the first high grayscale and a second sub-pattern emitting as the first low grayscale are alternatively disposed.
Inada teach:
Wherein the first display pattern is a mosaic pattern which is a first sub-pattern emitting as the first high grayscale and a second sub-pattern emitting as the first low grayscale are alternatively disposed, (at least refer to fig. 5, 7 and paragraph 119-120. Describes the output tone of pixel data that is written to the first region during the first display period is 186, and the output tone of pixel data that is written to the second region during the first display period is 255. Para. 120, describes: the output tone of pixel data that is written to the first region is low during the first display period. For this reason, assuming the luminance of the backlight 2 as 100%, the first region appears to be dark and grayish during the first display period. This causes the pattern that is displayed on the liquid crystal panel 1 during the first display period to be a white-and-gray checkered pattern).
Regarding the motivation of Claim 2, refer to the rejection of Claim 19.
Regarding Claim 3, SO discloses:
a first difference value of the second low grayscale and the first low grayscale is smaller than a second difference value of the second low grayscale and the first high grayscale, (at least refer to fig. 5, 8 and paragraphs 137, 132. Describes a low-grayscale pattern LGP and a high-grayscale pattern HGP can be displayed together. Here, the high grayscale can mean a grayscale that is larger than 63 G. Further, hereinafter, an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area. Para. 132, describes: the grayscale value and the luminance value can be in proportion to each other, and a low grayscale can mean a grayscale that is equal to or smaller than 63 G in a gamma curve on which the maximum grayscale is 255 G. Fig. 5 depicts data voltage value in correspondence to the grayscale value. It is inherent from fig. 5 that there is a greater difference in the secondary difference value).
SO does not explicitly disclose:
Wherein the first high grayscale is a maximum grayscale in which the display panel emits, the first low grayscale is a minimum grayscale in which the display panel emits
Inada teach:
Wherein the first high grayscale is a maximum grayscale in which the display panel emits, the first low grayscale is a minimum grayscale in which the display panel emits, (at least refer to fig. 8 and paragraph 89. Describes assuming that A is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the first region during the first display period, that B is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the second region during the first display period, that C is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the first region during the second display period, and that D is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the second region during the second display period)
Inada does not teach:
a first difference value of the second low grayscale and the first low grayscale is smaller than a second difference value of the second low grayscale and the first high grayscale
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Regarding Claim 4, SO discloses:
Wherein the first low grayscale is 0 grayscale level, and the second low grayscale is a grayscale level which is same or higher than 1 grayscale level, (at least refer to fig. 16 and paragraph 160. Describes a normal area which occurs in the second period P2 and on which the mura is displayed with the same luminance as the luminance value of the low-grayscale line data).
SO does not explicitly disclose:
Wherein the first low grayscale is 0 grayscale level
Inada teach:
Wherein the first low grayscale is 0 grayscale level, (at least refer to fig. 16 and paragraph 128. Describes a display (black display) at a minimum luminance (output tone=0) is carried out during the second display period in the second region)
Regarding the motivation of Claim 4, refer to the rejection of Claim 19.
Regarding Claim 15, SO does not disclose:
Wherein the first display pattern is a mosaic pattern which is a first sub-pattern emitting as the first high grayscale and a second sub-pattern emitting as the first low grayscale are alternatively disposed.
Inada teach:
Wherein the first display pattern is a mosaic pattern which is a first sub-pattern emitting as the first high grayscale and a second sub-pattern emitting as the first low grayscale are alternatively disposed, (at least refer to fig. 5, 7 and paragraph 119-120. Describes the output tone of pixel data that is written to the first region during the first display period is 186, and the output tone of pixel data that is written to the second region during the first display period is 255. Para. 120, describes: the output tone of pixel data that is written to the first region is low during the first display period. For this reason, assuming the luminance of the backlight 2 as 100%, the first region appears to be dark and grayish during the first display period. This causes the pattern that is displayed on the liquid crystal panel 1 during the first display period to be a white-and-gray checkered pattern).
Regarding the motivation of Claim 15, refer to the rejection of Claim 19.
Regarding Claim 16, SO discloses:
Wherein the first high grayscale is a maximum grayscale in which the display panel emits, the first low grayscale is a minimum grayscale in which the display panel emits, and a first difference value of the second low grayscale and the first low grayscale is smaller than a second difference value of the second low grayscale and the first high grayscale, (at least refer to fig. 5, 8 and paragraphs 137, 132. Describes a low-grayscale pattern LGP and a high-grayscale pattern HGP can be displayed together. Here, the high grayscale can mean a grayscale that is larger than 63 G. Further, hereinafter, an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area. Para. 132, describes: the grayscale value and the luminance value can be in proportion to each other, and a low grayscale can mean a grayscale that is equal to or smaller than 63 G in a gamma curve on which the maximum grayscale is 255 G. Fig. 5 depicts data voltage value in correspondence to the grayscale value. It is inherent from fig. 5 that there is a greater difference in the secondary difference value).
SO does not explicitly disclose:
Wherein the first high grayscale is a maximum grayscale in which the display panel emits, the first low grayscale is a minimum grayscale in which the display panel emits
Inada teach:
Wherein the first high grayscale is a maximum grayscale in which the display panel emits, the first low grayscale is a minimum grayscale in which the display panel emits, (at least refer to fig. 8 and paragraph 89. Describes assuming that A is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the first region during the first display period, that B is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the second region during the first display period, that C is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the first region during the second display period, and that D is the maximum luminance of an output tone with respect to an input tone of pixel data that is displayed in the second region during the second display period)
Inada does not teach:
a first difference value of the second low grayscale and the first low grayscale is smaller than a second difference value of the second low grayscale and the first high grayscale.
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987).
Regarding Claim 20, SO discloses:
Wherein the first data voltage corresponds to a maximum grayscale in which the display panel emits, the second data voltage corresponds to a minimum grayscale in which the display panel emits, and a first difference value of the third data voltage and the second data voltage is smaller than a second difference value of the third data voltage and the first data voltage, (at least refer to fig. 5, 8 and paragraphs 137, 132. Describes a low-grayscale pattern LGP and a high-grayscale pattern HGP can be displayed together. Here, the high grayscale can mean a grayscale that is larger than 63 G. Further, hereinafter, an area on which the low-grayscale line data are displayed in the display area AA is called a first display area, and an area on which the high-grayscale line data are displayed in the display area AA is called a second display area. Para. 132, describes: the grayscale value and the luminance value can be in proportion to each other, and a low grayscale can mean a grayscale that is equal to or smaller than 63 G in a gamma curve on which the maximum grayscale is 255 G. Fig. 5 depicts data voltage value in correspondence to the grayscale value. It is inherent from fig. 5 that there is a greater difference in the secondary difference value).
SO does not explicitly disclose:
a first difference value of the third data voltage and the second data voltage is smaller than a second difference value of the third data voltage and the first data voltage
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Allowable Subject Matter
Claims 5-8, 10-13, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 08/08/2026
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