Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application filed June 23, 2025. Claims 1-20 are presented for examination. Claims 1 and 20 are independent claims.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 10-2024-0088256 filed in Korea on July 4, 2024 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted June 23, 2025.
Information Disclosure Statement
The Applicant’s Information Disclosure Statement filed (June 23, 2025 and December 28, 2025) has been received, entered into the record, and considered.
Drawings
The drawings filed June 23, 2025 are accepted by the examiner.
Abstract
The abstract filed June 23, 2025 is accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 6, 8, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (EP 4447022 A1 English translation of prior art CN 117999601 A) in view of Ahmed et al. (US 20220198995 A1).
As to Claim 1:
Guo et al. discloses a display device (Guo, see Abstract, where Guo discloses a pixel circuit, a pixel driving circuit and a display device are provided. The pixel circuit includes a first light emitting control circuit, a light emitting element, a driving circuit and a light emitting gating circuit; the light emitting gating circuit is configured to form a current path between the second terminal of the driving circuit and the light emitting element under the control of the light emitting control voltage provided by the light emitting control voltage terminal in the light emitting phase according to the light emitting data voltage provided by the light emitting data voltage terminal under the control of the first control signal provided by the first control terminal, so as to control the driving circuit to control the light emitting element to emit light, or, to form a current path between the second terminal of the driving circuit and the light emitting element during the light emitting phase, to control the driving circuit to control the light emitting element to emit light) comprising: a plurality of pixel circuit (Guo, see paragraph [0109] lines 1-7, where Guo discloses that the pixel circuit described in the present disclosure, the capacitance value of C1 electrically connected to the drain electrode of T1 can be reduced, or C1 can be removed, which is beneficial to achieve high Pixels Per Inch (PPI, pixel density)) each including at least one pixel driving circuit part (Guo, see driving circuit 10 in figure 1) including a plurality of transistors (Guo, see T0 and T4 in figure 7A); a light-emitting element (Guo, see M1 in figure 7A) electrically connected to the pixel driving circuit part (Guo, see light emitting element M1 connected electrically to T0 in figure 7A) and including an anode electrode and a cathode electrode (Guo, see paragraph [0059] lines 36-38, where Guo discloses that light emitting element M1 has an anode and cathode); a first power supply voltage line which receives a power supply voltage of a high level (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40, where Guo discloses that when DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF); a second power supply voltage line which receives a power supply voltage of a low level (Guo, see T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1); a switching circuit part (Guo, see 122 in figures 2 and 7) electrically connected to the plurality of pixel circuit on a one-to-one basis (Guo, see 122 connected to T4, driving circuit 10 , first light emitting control circuit 11 and light emitting element E1 in figure 2) and including: a first switching element (Guo, see T2 in figure 2) connected to the first power supply voltage line (Guo, see VF in figure 2), wherein the first switching element (Guo, see T2 in figure 2) is turned on by a data voltage of a first voltage level (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40, where Guo discloses that when DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF); and a second switching element (Guo, see T3 in figure 2) connected to the second power supply voltage line (Guo, see EM1 in figure 2) wherein the second switching element is turned on by a data voltage of a second voltage level (Guo, see T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1) different from the first voltage level (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40 and T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that EMI is a low voltage and VF is a high voltage) ; and a data line (Guo, see DT in figure 2) electrically connected to the switching circuit part (Guo, see G1 in figure 2), wherein the data line provides the data voltage of the first voltage level or the data voltage of the second voltage level to the switching circuit part (Guo, see paragraph [0044] lines 8-25 and paragraph [0045] lines 27-44, where Guo discloses that the data writing-in phase, G1 provides a high-voltage signal, EM1 provides a high-voltage signal, T1 is turned on, so as to write the light emitting data voltage provided by DT into the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch; when the light emitting data voltage is a high voltage, T3 can be turned on during the data writing-in phase and the light emitting phase; when the light emitting data voltage is a low voltage, T2 can be turned on during the data writing in phase and the light emitting phase; In the light emitting phase, when T3 is turned on, EM2 and EM1 are connected, and the light emitting element E1 emits light for a long time; when T2 is turned on, EM2 and VF are connected, EM2 is connected to the light emitting control voltage HF, and the light emitting element E1 emits light for a short time at the high-frequency. At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure is working. When PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1 is passed, a higher turn-on voltage is required when the high voltage signal provided by EM1 passes through, so the demand for the first control signal provided by G1 is greater, which can be solved by the following solution. When DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF, and turn off T2 when HF is a low voltage; at the same time, T3 can be turned off when EM1 provides a high voltage signal, and T3 can be turned on when EM1 provides a low voltage signal).
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Guo differs from the claimed subject matter in that Guo does not explicitly disclose blocks as it pertains to pixel circuit blocks.
However in an analogous art, Ahmed discloses blocks (Ahmed, see 110 in figure 1 and paragraph [0041], where Ahmed discloses that array of red, green, and blue micro-LEDs 110 is electrically coupled to in-pixel driver circuits 108. As mentioned herein, in some examples, micro-LEDs 110 of display 102 may also include infrared micro-LEDs. Each individual micro-LED 110 corresponds to a different pixel ( or subpixel) of display 102 that is driven by in-pixel driver circuit 108. In some embodiments, on top of the micro-LEDs 110 (opposite substrate 106 and in-pixel driver circuits 108) is a transparent conductive film 112).
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It would have been obvious to one of ordinary skill in the art to modify the invention of Guo with Ahmed. One would be motivated to modify Guo by disclosing blocks as taught by Ahmed, and thereby delivering bright colors and rich black levels while consuming three to five times less power than other displays (Ahmed, see paragraph [0001]).
As to Claim 2:
Guo in view of Ahmed discloses that the display device of claim 1, wherein the switching circuit part selectively provides the power supply voltage of the high level or the power supply voltage of the low level to any one of the plurality of pixel circuit blocks electrically connected to the switching circuit part (Guo, see paragraph [0044] lines 8-25 and paragraph [0045] lines 27-44, where Guo discloses that the data writing-in phase, G1 provides a high-voltage signal, EM1 provides a high-voltage signal, T1 is turned on, so as to write the light emitting data voltage provided by DT into the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch; when the light emitting data voltage is a high voltage, T3 can be turned on during the data writing-in phase and the light emitting phase; when the light emitting data voltage is a low voltage, T2 can be turned on during the data writing in phase and the light emitting phase; In the light emitting phase, when T3 is turned on, EM2 and EM1 are connected, and the light emitting element E1 emits light for a long time; when T2 is turned on, EM2 and VF are connected, EM2 is connected to the light emitting control voltage HF, and the light emitting element E1 emits light for a short time at the high-frequency. At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure is working. When PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1 is passed, a higher turn-on voltage is required when the high voltage signal provided by EM1 passes through, so the demand for the first control signal provided by G1 is greater, which can be solved by the following solution. When DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF, and turn off T2 when HF is a low voltage; at the same time, T3 can be turned off when EM1 provides a high voltage signal, and T3 can be turned on when EM1 provides a low voltage signal).
As to Claim 3:
Guo in view of Ahmed discloses that the display device of claim 1, wherein the first switching element is turned off by the data voltage of the second voltage level and the second switching element is turned off by the data voltage of the first voltage level (Guo, see T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1).
As to Claim 6:
Guo in view of Ahmed discloses that the display device of claim 1, wherein a power line to which a common voltage is applied is connected to the cathode electrode (Guo, see paragraph [0059] lines 36-38, where Guo discloses that light emitting element M1 has an anode and cathode and the cathode of the micro-LED M1 is electrically connected to the low voltage terminal VSS;, and the power supply voltage is a driving voltage having a voltage level higher than a voltage level of the common voltage (Guo, see paragraph [0059] lines 30-38, where Guo discloses that the gate electrode of the fourth transistor T4 is electrically connected to the second light emitting control terminal EM2, the source electrode of the fourth transistor T4 is electrically connected to the second terminal of the driving circuit 10, and the drain electrode of the fourth transistor T4 is electrically connected to the anode of the micro-LED M1, the anode of M1 receives the voltage of T4 which is higher than VSS).
As to Claim 8:
Guo in view of Ahmed discloses the display device of claim 1, further comprising: an output power connection line connecting the anode electrode and the switching circuit part (Guo, see EM2 and T4 proving voltage to anode of M1 in figure 7A), wherein the output power connection line selectively receives the power supply voltage of the high level or the power supply voltage of the low level through the switching circuit part (Guo, see paragraph [0044] lines 8-25 and paragraph [0045] lines 27-44, where Guo discloses that the data writing-in phase, G1 provides a high-voltage signal, EM1 provides a high-voltage signal, T1 is turned on, so as to write the light emitting data voltage provided by DT into the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch; when the light emitting data voltage is a high voltage, T3 can be turned on during the data writing-in phase and the light emitting phase; when the light emitting data voltage is a low voltage, T2 can be turned on during the data writing in phase and the light emitting phase; In the light emitting phase, when T3 is turned on, EM2 and EM1 are connected, and the light emitting element E1 emits light for a long time; when T2 is turned on, EM2 and VF are connected, EM2 is connected to the light emitting control voltage HF, and the light emitting element E1 emits light for a short time at the high-frequency. At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure is working. When PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1 is passed, a higher turn-on voltage is required when the high voltage signal provided by EM1 passes through, so the demand for the first control signal provided by G1 is greater, which can be solved by the following solution. When DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF, and turn off T2 when HF is a low voltage; at the same time, T3 can be turned off when EM1 provides a high voltage signal, and T3 can be turned on when EM1 provides a low voltage signal).
As to Claim 9:
Guo in view of Ahmed discloses that the display device of claim 1, further comprising: an output power connection line connecting the cathode electrode and the switching circuit part, wherein the output power connection line selectively receives the power supply voltage of the high level or the power supply voltage of the low level through the switching circuit part (Guo, see paragraph [0044] lines 8-25 and paragraph [0045] lines 27-44, where Guo discloses that the data writing-in phase, G1 provides a high-voltage signal, EM1 provides a high-voltage signal, T1 is turned on, so as to write the light emitting data voltage provided by DT into the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch; when the light emitting data voltage is a high voltage, T3 can be turned on during the data writing-in phase and the light emitting phase; when the light emitting data voltage is a low voltage, T2 can be turned on during the data writing in phase and the light emitting phase; In the light emitting phase, when T3 is turned on, EM2 and EM1 are connected, and the light emitting element E1 emits light for a long time; when T2 is turned on, EM2 and VF are connected, EM2 is connected to the light emitting control voltage HF, and the light emitting element E1 emits light for a short time at the high-frequency. At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure is working. When PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1 is passed, a higher turn-on voltage is required when the high voltage signal provided by EM1 passes through, so the demand for the first control signal provided by G1 is greater, which can be solved by the following solution. When DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF, and turn off T2 when HF is a low voltage; at the same time, T3 can be turned off when EM1 provides a high voltage signal, and T3 can be turned on when EM1 provides a low voltage signal).
As to Claim 20:
Guo et al. discloses an electronic device (Guo, see Abstract, where Guo discloses a pixel circuit, a pixel driving circuit and a display device are provided. The pixel circuit includes a first light emitting control circuit, a light emitting element, a driving circuit and a light emitting gating circuit; the light emitting gating circuit is configured to form a current path between the second terminal of the driving circuit and the light emitting element under the control of the light emitting control voltage provided by the light emitting control voltage terminal in the light emitting phase according to the light emitting data voltage provided by the light emitting data voltage terminal under the control of the first control signal provided by the first control terminal, so as to control the driving circuit to control the light emitting element to emit light, or, to form a current path between the second terminal of the driving circuit and the light emitting element during the light emitting phase, to control the driving circuit to control the light emitting element to emit light) comprising: a display device (Guo, see paragraph [0001], where Guo discloses that the disclosure relates to the field of display technology, in particular to a pixel circuit, a pixel driving circuit and a display device) and a processor which controls the display device (Guo, see paragraph [0015] lines 13-28, where Guo discloses that the pixel circuit further includes a data writing-in circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit and a third capacitor; the data writing-in circuit is electrically connected to a second control terminal, a data line and the first terminal of the driving circuit, and is configured to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of a second control signal provided by the second control terminal; the compensation control circuit is electrically connected to a third control terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control to connect the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a third control signal provided by the third control terminal), wherein the display device includes: a plurality of pixel circuit (Guo, see paragraph [0109] lines 1-7, where Guo discloses that the pixel circuit described in the present disclosure, the capacitance value of C1 electrically connected to the drain electrode of T1 can be reduced, or C1 can be removed, which is beneficial to achieve high Pixels Per Inch (PPI, pixel density)) each including at least one pixel driving circuit part (Guo, see driving circuit 10 in figure 1) including a plurality of transistors (Guo, see T0 and T4 in figure 7A); a light-emitting element (Guo, see M1 in figure 7A) electrically connected to the pixel driving circuit part (Guo, see light emitting element M1 connected electrically to T0 in figure 7A) and including an anode electrode and a cathode electrode (Guo, see paragraph [0059] lines 36-38, where Guo discloses that light emitting element M1 has an anode and cathode); a first power supply voltage line which receives a power supply voltage of a high level (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40, where Guo discloses that when DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF); a second power supply voltage line which receives a power supply voltage of a low level (Guo, see T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1); a switching circuit part (Guo, see 122 in figures 2 and 7) electrically connected to the plurality of pixel circuit on a one-to-one basis (Guo, see 122 connected to T4, driving circuit 10 , first light emitting control circuit 11 and light emitting element E1 in figure 2) and including: a first switching element (Guo, see T2 in figure 2) connected to the first power supply voltage line (Guo, see VF in figure 2), wherein the first switching element (Guo, see T2 in figure 2) is turned on by a data voltage of a first voltage level (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40, where Guo discloses that when DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF); and a second switching element (Guo, see T3 in figure 2) connected to the second power supply voltage line (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40 and T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that EMI is a low voltage and VF is a high voltage), wherein the second switching element is turned on by a data voltage of a second voltage level (Guo, see T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1) different from the first voltage level (Guo, see VF and T2 in figure 2 and figure 7A and paragraph [0045] lines 37-40 and T3 and EM1 in figures 2 and 7 and paragraph [0045] lines 29-32, where Guo discloses that EMI is a low voltage and VF is a high voltage); and a data line (Guo, see DT in figure 2) electrically connected to the switching circuit part (Guo, see G1 in figure 2), wherein the data line provides the data voltage of the first voltage level or the data voltage of the second voltage level to the switching circuit part (Guo, see paragraph [0044] lines 8-25 and paragraph [0045] lines 27-44, where Guo discloses that the data writing-in phase, G1 provides a high-voltage signal, EM1 provides a high-voltage signal, T1 is turned on, so as to write the light emitting data voltage provided by DT into the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch; when the light emitting data voltage is a high voltage, T3 can be turned on during the data writing-in phase and the light emitting phase; when the light emitting data voltage is a low voltage, T2 can be turned on during the data writing in phase and the light emitting phase; In the light emitting phase, when T3 is turned on, EM2 and EM1 are connected, and the light emitting element E1 emits light for a long time; when T2 is turned on, EM2 and VF are connected, EM2 is connected to the light emitting control voltage HF, and the light emitting element E1 emits light for a short time at the high-frequency. At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure is working. When PAM emits light for a long time, the high voltage signal provided by DT needs to enter the gate electrode of T3 through T1 to turn on T3, so that the high voltage signal or the low voltage signal provided by EM1 is passed, a higher turn-on voltage is required when the high voltage signal provided by EM1 passes through, so the demand for the first control signal provided by G1 is greater, which can be solved by the following solution. When DT provides a high voltage signal, the light emitting data voltage provided by DT is lower, and the light emitting data voltage can turn on T2 when HF is a high voltage, provide a high voltage signal for EM2 through HF, and turn off T2 when HF is a low voltage; at the same time, T3 can be turned off when EM1 provides a high voltage signal, and T3 can be turned on when EM1 provides a low voltage signal).
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Guo differs from the claimed subject matter in that Guo does not explicitly disclose blocks as it pertains to pixel circuit blocks.
However in an analogous art, Ahmed discloses blocks (Ahmed, see 110 in figure 1 and paragraph [0041], where Ahmed discloses that array of red, green, and blue micro-LEDs 110 is electrically coupled to in-pixel driver circuits 108. As mentioned herein, in some examples, micro-LEDs 110 of display 102 may also include infrared micro-LEDs. Each individual micro-LED 110 corresponds to a different pixel ( or subpixel) of display 102 that is driven by in-pixel driver circuit 108. In some embodiments, on top of the micro-LEDs 110 (opposite substrate 106 and in-pixel driver circuits 108) is a transparent conductive film 112).
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It would have been obvious to one of ordinary skill in the art to modify the invention of Guo with Ahmed. One would be motivated to modify Guo by disclosing blocks as taught by Ahmed, and thereby delivering bright colors and rich black levels while consuming three to five times less power than other displays (Ahmed, see paragraph [0001]).
Allowable Subject Matter
Claims 4, 5, 7 and 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 4, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein when the first switching element is turned on, the second switching element is turned off, and when the first switching element is turned off, the second switching element is turned on”.
Referring to claim 5, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein when the first switching element is a PMOS transistor, the second switching element is a NMOS transistor, and when the first switching element is a NMOS transistor, the second switching element is a PMOS transistor”.
Referring to claim 7, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the plurality of transistors include a switching transistor including a gate electrode controlled by a light-emitting control signal, a source electrode, and a drain electrode, further comprising: an output power connection line connecting the source electrode of the switching transistor and the switching circuit part, wherein the output power connection line selectively receives the power supply voltage of the high level or the power supply voltage of the low level through the switching circuit part”.
Referring to claim 10 and dependent claims 11-17, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “a separator disposed on the pixel driving circuit part and surrounding the pixel circuit blocks in a plan view, wherein the cathode electrode is disconnected by the separator”.
Referring to claim 18 and dependent claim 19, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the pixel driving circuit part includes: an inorganic insulating layer disposed on a substrate; a first organic insulating layer disposed on the inorganic insulating layer; a second organic insulating layer disposed on the first organic insulating layer and defining a first sub-opening exposing at least a portion of the output power connection line; a pixel defining layer disposed on the second organic insulating layer and defining a second sub-opening spatially connected to the first sub-opening, wherein the pixel defining layer includes an engraved pattern surrounding the pixel circuit blocks in a plan view”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Ogawa (US 12277897 B2) discloses a display device includes a plurality of light-emitting elements arrayed in a display region, a first pixel circuit and a second pixel circuit coupled to each of the light-emitting elements, a first drive transistor provided to the first pixel circuit and configured to supply a first drive current to the light-emitting element, a second drive transistor provided to the second pixel circuit and configured to supply a second drive current to the light-emitting element, a drive circuit configured to supply a video signal to the first drive transistor and the second drive transistor, a first coupling switching transistor provided between the first drive transistor and the light-emitting element, and a second coupling switching transistor provided between the second drive transistor and the light-emitting element. The first coupling switching transistor and the second coupling switching transistor are turned off in a non-emission period of the light-emitting element.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/Primary Examiner, Art Unit 2624
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