DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/24/2025 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12372978. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the 978 patent encompass the current claims as outlined below.
With respect to claim 1
The 978 patent claims: A circuit board in communication with one or more device controllers, the circuit board (see identical language in claim 1 of the 978 patent) comprising:
a processor device (see identical language in claim 1 of the 978 patent);
a plurality of sensor assemblies electrically connected to the processor device and configured to receive sensor information from one or more sensors (see identical language in claim 1 of the 978 patent); and
one or more memory devices storing computer-readable instructions that when executed cause the processor device to cause the circuit board (see claim 1 of the 978 patent) to be:
for a first direction of travel or a first phase of flight of an aircraft, a primary circuit board in a control hierarchy relative to a second circuit board of the aircraft (see identical language in claim 1 of the 978 patent); and
for a second direction of travel or a second phase of flight of the aircraft, a redundant circuit board in the control hierarchy relative to the second circuit board (see identical language in claim 1 of the 978 patent).
Claims 2-20 correspond to claims 2-20 of the 978 patent respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0378936 (Delielsson et al.) teaches: A circuit board (see at least Fig 1-3; S(1-4) and #35; and ¶0053-56) in communication with one or more device controllers (see at least Fig 1-3; S(1-4), #35, ACT, and AVS; and ¶0053-56), the circuit board (S(1-4) and #35) comprising: a processor device (see at least Fig 3; #3; and ¶0057); a plurality of sensor assemblies electrically connected to the processor device and configured to receive sensor information from one or more sensors (see at least Fig 3; #5; and ¶0057; Discussing the I/O interface connecting to sensors.); and one or more memory devices storing computer-readable instructions (see at least Fig 3; #4; and ¶0057) that when executed cause the processor device (see at least Fig 3; #3; and ¶0057).
US 996481 (Danielsson et al.) teaches a decentralized system.
US 20190235090 (Lott) teaches using different GPS receivers depending on the UAVs orientation.
US 2019/0227538 (Lassini et al.) teaches a UAV with redundant processing systems.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F WHALEN whose telephone number is (571)270-7747. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Peter Nolan can be reached at (571) 270-7016. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL F. WHALEN
Examiner
Art Unit 3661
/M.F.W./Examiner, Art Unit 3661
/PETER D NOLAN/Supervisory Patent Examiner, Art Unit 3661
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