Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 9, 10-13,15-17, 19, 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. US 20250232729.
Regarding claims 1, 15, 20, Kim et al. US 20250232729., figs. 1, 4, 14, discloses a display device comprising: a base layer (Sub) in which a display region and a non-display region adjacent to the display region are defined (The display panel 110 may include a display area DA in which images are displayed and a non-display area NDA in which no image is displayed.
[0082] The non-display area NDA may be an outer area of the display area DA and be referred to as a bezel area. The non-display area NDA may be an area visible from the front of the display apparatus 100 or an area that is bent and not visible from the front of the display apparatus 100); a circuit layer comprising a scan clock line in the non-display region and extending in a first direction, and a scan driver connected to the scan clock line; and a light-emitting element on the circuit layer ([0223] The light emitting element ED may include a first electrode E1, which corresponds to the anode electrode (or cathode electrode), a emission layer EL formed on the first electrode E1, and a second electrode E2 formed on the emission layer EL and corresponding to the cathode electrode (or anode electrode)), and comprising a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer, wherein a first opening overlapping the scan clock line is defined in the second electrode (The gate electrode GE and the semiconductor layer SEMI may overlap each other, with the gate insulation film GI interposed therebetween. The source electrode SE may be formed on an insulation layer INS to contact one side of the semiconductor layer SEMI, and the drain electrode DE may be formed on the insulation layer INS to contact the other side of the semiconductor layer SEMI. For example, the semiconductor layer may include an oxide semiconductor layer or a low-temperature polysilicon semiconductor layer, but aspects of the present disclosure are not limited thereto. The light emitting element ED may include a first electrode E1, which corresponds to the anode electrode (or cathode electrode), a emission layer EL formed on the first electrode E1, and a second electrode E2 formed on the emission layer EL and corresponding to the cathode electrode (or anode electrode)).
Regarding claims 2, 10, 16, 17, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 1, wherein the second electrode comprises a first sub-electrode and a second sub-electrode that are spaced apart from each other with respect to the first opening; and or wherein a second opening overlapping the emission clock line is defined in the second electrode, and wherein the first opening and the second opening are spaced apart from each other in a second direction crossing the first direction (the emission layer EL may be disposed on the first electrode E1 in an emission area defined by a bank BANK. The emission layer EL may be formed in the order of hole-related layer, emission layer, and electron-related layer, or its reverse order, on the first electrode E1. The second electrode E2 may be formed to face the first electrode E1, with the emission layer EL disposed therebetween).
Regarding claim 3, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 2, further comprising a connection electrode configured to electrically connect the first sub-electrode and the second sub-electrode to each other, wherein the first sub-electrode and the second sub-electrode each are in contact with the connection electrode [0238] A touch buffer layer T-BUF may be disposed on the encapsulation layer ENCAP. The touch buffer layer T-BUF may be positioned between the touch sensor metal including the touch electrodes X-TE and Y-TE and the touch electrode connection lines X-CL and Y-CL, and the second electrode E2 of the light emitting element ED).[0239] The touch buffer layer T-BUF may be formed to maintain a predetermined distance (e.g., 1 μm) between the touch sensor metal and the second electrode E2 of the light emitting element ED, but aspects of the present disclosure are not limited thereto. Thus, it is possible to reduce or prevent the parasitic capacitance formed between the touch sensor metal and the second electrode E2 of the light emitting element ED, and thus, reduce or prevent deterioration of touch sensitivity due to parasitic capacitance).
Regarding claim 9, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 1, wherein the circuit layer further comprises an emission clock line in the non-display region and extending in the first direction, and an emission driver connected to the emission clock line (see pars. 122, 123, 133-136).
Regarding claim 11, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 9, wherein the emission driver and the scan driver are spaced apart from each other with respect to the display region (The line emission signals EM[1], EM[2], EM[3], and EM[4] may be supplied to the display panel 110 through the corresponding subpixel lines, and each line emission signal EM[1], EM[2], EM[3], and EM[4] may include one or more emission signals based on the structure of the subpixel SP.The scan driving circuit SCD may operate based on scan clocks SCLKs, a scan start signal SVST, a low-potential scan voltage VSL, and a high-potential scan voltage VSH to generate a line scan signals SCAN[1], SCAN[2], SCAN[3], and SCAN[4]).
Regarding claim 12, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 10, further comprising an insulation layer in each of the first opening and the second opening (The gate electrode GE and the semiconductor layer SEMI may overlap each other, with the gate insulation film GI interposed therebetween. The source electrode SE may be formed on an insulation layer INS to contact one side of the semiconductor layer SEMI, and the drain electrode DE may be formed on the insulation layer INS to contact the other side of the semiconductor layer SEMI. For example, the semiconductor layer may include an oxide semiconductor layer or a low-temperature polysilicon semiconductor layer, but aspects of the present disclosure are not limited thereto).
Regarding claim 13, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 1, further comprising a power supply line in the non-display region, and configured to apply a driving voltage to the second electrode (par. 13).
Regarding claim 19, Kim et al. US 20250232729., figs. 1, 4, 14, discloses the display device of claim 15, wherein the scan clock line extends in a first direction, and the opening is defined to be parallel to the scan clock line in the first direction (see par. 51, and fig. 14).
Allowable Subject Matter
Claims 4-8, 14, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest the display device of claim 3, further comprising: an insulation film in which a contact opening that exposes at least a portion of the connection electrode is defined; and a separator in the contact opening; and/or the display device of claim 4, wherein the contact opening comprises a first contact opening and a second contact opening that are spaced apart from each other with respect to the first opening, and wherein the separator comprises a first separator in the first contact opening, and a second separator in the second contact opening; and/or the display device of claim 13, wherein the non-display region comprises a first non-display region in which the power supply line is, and a second non-display region in which the first opening is positioned, and wherein the second non-display region is between the first non-display region and the display region; and/or the display device of claim 17, wherein in a first contact region adjacent to the first separator, a lower surface of the first sub-electrode is in contact with an upper surface of the connection electrode, and wherein in a second contact region adjacent to the second separator, a lower surface of the second sub-electrode is in contact with an upper surface of the connection electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN N CHOW/Primary Examiner, Art Unit 2627
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