DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12,381,551.
Although the claims at issue are not identical (a method vs a structure), they are not patentably distinct from each other because the instant application claims structure is not patentably distinct from the method claims of US Patent No. 12,381,551. The structure of the instant application claims is intended to perform the steps of the method of claims of US Patent No. 12,381,551. The structural claim does not include additional limitations that render the claim non-obvious in view of the method claim.
Comparing the instant application with Patent 12,381,551 as follows
Instant application 19/247229
U.S. Patent No. 12,381,551
1. A semiconductor device comprising: a decoupling capacitance system configured to decouple voltage variations in a first voltage drop between a first reference voltage rail and a second reference voltage rail, the decoupling capacitance system including: a decoupling capacitance circuit; and a filtered biasing circuit, wherein an unswitched series electrical connection couples the decoupling capacitance circuit and the filtered biasing circuit between the first reference voltage rail and the second reference voltage rail.
1. A method of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails, the method comprising: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.
2. The semiconductor device of claim 1, wherein: the unswitched series electrical connection includes: a first electrical connection between the decoupling capacitance circuit and the first or second reference voltage rail, and second electrical connection between the decoupling capacitance circuit and a first node; and a third electrical connection between the filtered biasing circuit and the first node, and a fourth electrical connection correspondingly between the filtered biasing circuit the second or first reference voltage rail.
2. The method of claim 1, wherein the making an unswitched series electrical coupling includes: electrically coupling the decap circuit between the first or second reference voltage rail and a first node; and electrically coupling the filtered biasing circuit between the first node and correspondingly the second or first reference voltage rail.
3. The semiconductor device of claim 2, wherein: the filtered biasing circuit includes a first filter and a second filter; each of the first filter and the second filter is a high pass filter, or each of the first filter and the second filter is a low pass filter; first filter is electrically coupled between (1) the first or second reference voltage rail and (2) the first node; and the second filter is electrically coupled between the first and second reference voltage rails.
3. The method of claim 2, wherein the electrically coupling the filtered biasing circuit includes: electrically coupling one or more components to form a first filter; electrically coupling one or more components to form a second filter; configuring each of the first filter and the second filter as a same type of filter including: configuring each of the first filter and the second filter as a high pass filter; or configuring each of the first filter and the second filter as a low pass filter; electrically coupling the first filter between (1) the first or second reference voltage rails and (2) the first node; and electrically coupling the second filter between the first and second reference voltage rails.
4. The semiconductor device of claim 3, wherein: the first filter includes: first and second components coupled to each other at a second node and in series between (1) the first or second reference voltage rail and (2) the first node; the second filter includes: third and fourth components coupled to each other at a third node and in series between the first and second reference voltage rails; a first control terminal of the filtered biasing circuit is coupled to the second node; and a second control terminal of the filtered biasing circuit is coupled to the third node.
4. The method of claim 3, wherein: the electrically coupling the first filter includes: electrically coupling first and second components to each other at a second node and in series between (1) the first or second reference voltage rails and (2) the first node; the electrically coupling the second filter includes: electrically coupling third and fourth components to each other at a third node and in series between the first and second reference voltage rails; and the electrically coupling the filtered biasing circuit further includes: electrically coupling a first control terminal of the filtered biasing circuit to the second node; and electrically coupling a second control terminal of the filtered biasing circuit to the third node.
5. The semiconductor device of claim 4, wherein: the first filter further includes: a first capacitor as the first component; and a first resistor as the second component; and the second filter further includes: a second capacitor as the third component; and a second resistor as the fourth component.
5. The method of claim 4, wherein: the electrically coupling the first filter further includes: using a first capacitor as the first component; and using a first resistor as the second component; and the electrically coupling the second filter further includes: using a second capacitor as the third component; and using a second resistor as the fourth component.
6. The semiconductor device of claim 4, wherein: the filtered biasing circuit further includes: a first switch and a second switch coupled in parallel between the first node and the second reference voltage rail; or the first switch and the second switch coupled in parallel between the first node and the first reference voltage rail; the first control terminal is a control input of the first switch; and the second control terminal is a control input of the second switch.
6. The method of claim 4, wherein: the electrically coupling the filtered biasing circuit further includes: electrically coupling each of a first switch and a second switch in parallel between the first node and the second reference voltage rail; or electrically coupling each of the first switch and the second switch in parallel between the first node and the first reference voltage rail; the first control terminal being a control input of the first switch; and the second control terminal being a control input of the second switch.
7. The semiconductor device of claim 6, wherein: the first switch is an N-type metal-oxide-semiconductor field-effect transistor (NFET), the second switch is a P-type MOSFET (PFET), and the NFET and the PFET are coupled in parallel between the first node and the second reference voltage rail; or the first switch is an N-type metal-oxide-semiconductor field-effect transistor (NFET), the second switch is a P-type MOSFET (PFET), and the NFET and the PFET are coupled in parallel between the first node and the first reference voltage rail.
7. The method of claim 6, wherein: the electrically coupling each of a first switch and a second switch in parallel between the first node and the second reference voltage rail includes: electrically coupling an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) as the first switch and a P-type MOSFET (PFET) as the second switch in parallel between the first node and the second reference voltage rail; or the electrically coupling each of the first switch and the second switch in parallel between the first node and the first reference voltage rail includes: electrically coupling an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) as the first switch and a P-type MOSFET (PFET) as the second switch in parallel between the first node and the first reference voltage rail.
8. The semiconductor device of claim 1, wherein: the filtered biasing circuit includes: an N-type MOSFET (NFET) and a P-type MOSFET (PFET) coupled in parallel between an input and an output of the filtered biasing circuit.
8. The method of claim 1, wherein the electrically coupling one or more components to form a filtered biasing circuit includes: electrically coupling metal-oxide-semiconductor field-effect transistor (MOSFETs) including: electrically coupling an N-type MOSFET (NFET) and a P-type MOSFET (PFET) in parallel between an input and an output of the filtered biasing circuit.
9. The semiconductor device of claim 8, wherein: the filtered biasing circuit further includes: first and second components coupled to each other at a first node and in series between (1) the first or second reference voltage rail and (2) a second node as a first filter; and third and fourth components coupled to each other at a third node and in series between the first and second reference voltage rails as a second filter; and either: a gate terminal of the NFET is coupled to the first node, and a gate terminal of the PFET is coupled to the third node; or a gate terminal of the NFET is coupled to the third node, and a gate terminal of the PFET is coupled to the first node.
9. The method of claim 8, wherein the electrically coupling one or more components to form a filtered biasing circuit further includes: electrically coupling first and second components to each other at a first node and in series between (1) the first or second reference voltage rails and (2) a second node as a first filter; electrically coupling third and fourth components to each other at a third node and in series between the first and second reference voltage rails as a second filter; and either: electrically coupling a gate terminal of the NFET to the first node and a gate terminal of the PFET to the third node; or electrically coupling a gate terminal of the NFET to the third node and a gate terminal of the PFET to the first node.
10. The semiconductor device of claim 1, wherein: the decoupling capacitance circuit includes: an N-type MOSFET (NFET) electrically coupled in a capacitor configuration between (1) a first node and (2) the first or second reference voltage rail.
10. The method of claim 1, wherein the electrically coupling one or more components to form a decoupling capacitance (decap) circuit includes: electrically coupling metal-oxide-semiconductor field-effect transistor (MOSFETs) including: electrically coupling an N-type MOSFET (NFET) in a capacitor configuration between (1) a first node and (2) the first and second reference voltage rails.
11. The semiconductor device of claim 10, wherein: the filtered biasing circuit includes a first high pass filter (HPF) and a second HPF; a gate terminal of the NFET is coupled to the first reference voltage rail; and source and drain terminals of the NFET are coupled to the first node.
11. The method of claim 10, wherein: the electrically coupling one or more components to form a filtered biasing circuit includes: electrically coupling one or more components to form a first high pass filter (HPF); and electrically coupling one or more components to form a second HPF; and the electrically coupling an N-type MOSFET (NFET) in a capacitor configuration includes: electrically coupling a gate terminal of the NFET to the first reference voltage rail; and electrically coupling source and terminals of the NFET to the first node.
12. The semiconductor device of claim 10, wherein: the filtered biasing circuit includes a first low pass filter (LPF) and a second LPF; a gate terminal of the NFET is coupled to the second reference voltage rail; and source and terminals of the NFET are coupled to the first node.
12. The method of claim 10, wherein: the electrically coupling one or more components to form a filtered biasing circuit includes: electrically coupling one or more components to form a first low pass filter (LPF); and electrically coupling one or more components to form a second LPF; and the electrically coupling an N-type MOSFET (NFET) in a capacitor configuration includes: electrically coupling a gate terminal of the NFET to the second reference voltage rail; and electrically coupling source and terminals of the NFET to the first node.
13. A semiconductor device comprising: a decoupling capacitance circuit; a filtered biasing circuit including: a metal-oxide-semiconductor field-effect transistor (MOSFET) of N-type (NFET) and a MOSFET of P-type (PFET) coupled in parallel between an input and an output of the filtered biasing circuit; first and second components coupled to each other at a first node and in series between (1) a first reference voltage rail or a second reference voltage rail and (2) a second node as a first filter; and third and fourth components coupled to each other at a third node and in series between the first reference voltage rail and the second reference voltage rail as a second filter, wherein either: a gate terminal of the NFET is coupled to the first node, and a gate terminal of the PFET is coupled to the third node; or a gate terminal of the NFET is coupled to the third node and a gate terminal of the PFET is coupled to the first node; and an unswitched series electrical connection coupling the decoupling capacitance circuit and the filtered biasing circuit between the first reference voltage rail and the second reference voltage rail.
13. A method of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails, the method comprising: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit including: electrically coupling an metal-oxide-semiconductor field-effect transistor (MOSFET) of N-type (NFET) and a MOSFET of P-type (PFET) in parallel between an input and an output of the filtered biasing circuit; electrically coupling first and second components to each other at a first node and in series between (1) the first or second reference voltage rails and (2) a second node as a first filter; electrically coupling third and fourth components to each other at a third node and in series between the first and second reference voltage rails as a second filter; and either: electrically coupling a gate terminal of the NFET to the first node and a gate terminal of the PFET to the third node; or electrically coupling a gate terminal of the NFET to the third node and a gate terminal of the PFET to the first node; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.
14. The semiconductor device of claim 13, wherein, in the filtered biasing circuit: the gate terminal of the NFET is coupled to the first node, a gate terminal of the PFET is coupled to the third node, and each of the first filter and the second filter is a high pass filter; or the gate terminal of the NFET is coupled to the third node, a gate terminal of the PFET is coupled to the first node, and each of the first filter and the second filter is a low pass filter.
14. The method of claim 13, wherein the electrically coupling the filtered biasing circuit further includes: where the gate terminal of the NFET is electrically coupled to the first node and a gate terminal of the PFET to the third node, configuring each of the first filter and the second filter as a high pass filter; or where the gate terminal of the NFET is electrically coupled to the third node and a gate terminal of the PFET to the first node, configuring each of the first filter and the second filter as a low pass filter.
15. The semiconductor device of claim 13, wherein: the decoupling capacitance circuit includes: an NFET coupled in a capacitor configuration between (1) the second node and (2) the first or second reference voltage rail.
15. The method of claim 13, wherein the electrically coupling one or more components to form a decoupling capacitance (decap) circuit includes: electrically coupling metal-oxide-semiconductor field-effect transistor (MOSFETs) including: electrically coupling an N-type MOSFET (NFET) in a capacitor configuration between (1) the second node and (2) the first and second reference voltage rails.
16. A semiconductor device comprising: active regions including doped areas of a substrate; source/drain (S/D) regions including first doped areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components; gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; via-to-gate/MD (VGD) structures representing fifth transistor-components over corresponding ones of the gate lines and the MD contact structures, the VGD structures electrically coupling: a first set of the first to fourth transistor-components as an alpha metal-oxide- semiconductor field-effect transistor (MOSFET); and a second set of the first to fourth transistor-components as beta MOSFETs; and metallization segments and interconnection structures arranged in interleaved layers over corresponding areas some of which correspondingly include the alpha MOSFET and the beta MOSFETs, wherein: the metallization segments and interconnection structures form first and second capacitors, first and second resistors, and first and second reference voltage rails; and the metallization segments and interconnection structures couple: the alpha MOSFET as a decoupling capacitance circuit; the first and second capacitors, the first and second resistors, and the beta MOSFETs as a filtered biasing circuit; and the decoupling capacitance circuit and the filtered biasing circuit as an unswitched connection coupled in series between the first reference voltage rail and the second reference voltage rail.
16. A method of forming semiconductor device that includes a decoupling capacitance (decap) system, the method comprising: forming active regions including doping areas of a substrate; forming source/drain (S/D) regions including doping first areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components; forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; forming via-to-gate/MD (VGD) structures representing fifth transistor-components over corresponding ones of the gate lines and the MD contact structures, the VGD structures electrically coupling: a first set of the first to fourth transistor-components as an alpha metal-oxide-semiconductor field-effect transistor (MOSFETs); and a second set of the first to fourth transistor-components as beta MOSFETs; and forming metallization segments and interconnection structures on an interleaved layer basis over corresponding areas some of which correspondingly include the alpha MOSFET and the beta MOSFETs; and wherein: the forming metallization segments and interconnection structures results in first and second capacitors, first and second resistors, and first and second reference voltage rails; and the forming metallization segments and interconnection structures electrically couples: the alpha MOSFET as a decoupling capacitance (decap) circuit; the first and second capacitors, the first and second resistors and the beta MOSFETs as a filtered biasing circuit; and the decap circuit and the filtered biasing circuit as unswitched in series between the first and second reference voltage rails.
17. The semiconductor device of claim 16, wherein: the metallization segments and interconnection structures further couple: the decoupling capacitance circuit between the first or second reference voltage rail and a first node; and the filtered biasing circuit between the first node and correspondingly the second or first reference voltage rail.
17. The method of claim 16, wherein the forming metallization segments and interconnection structures further electrically couples: the decap circuit between the first or second reference voltage rail and a first node; and the filtered biasing circuit between the first node and correspondingly the second or first reference voltage rail.
18. The semiconductor device of claim 17, wherein: the metallization segments and interconnection structures further couple: the first capacitor and the first resistor as a first filter; the second capacitor and the second resistor as a second filter; the first filter between (1) the first or second reference voltage rail and (2) the first node; and the second filter between the first and second reference voltage rails.
18. The method of claim 17, wherein the forming metallization segments and interconnection structures further electrically couples: the first capacitor and the first resistor to form a first filter; the second capacitor and the second resistor to form a second filter; the first filter between (1) the first or second reference voltage rails and (2) the first node; and the second filter between the first and second reference voltage rails.
19. The semiconductor device of claim 18, wherein: the metallization segments and interconnection structures further couple: each of the first filter and the second filter as a high pass filter; or each of the first filter and the second filter as a low pass filter.
19. The method of claim 18, wherein the forming metallization segments and interconnection structures further electrically couples: each of the first filter and the second filter as a high pass filter; or each of the first filter and the second filter as a low pass filter.
20. The semiconductor device of claim 18, wherein: the metallization segments and interconnection structures further couple: the first capacitor and the first resistor of the first filter to each other at a second node and in series between (1) the first or second reference voltage rail and (2) the first node; and the second capacitor and the second resistor of the second filter to each other at a third node and in series between the first and second reference voltage rail; and either: a gate terminal of a first one of the beta MOSFETs is coupled to the second node, and a gate terminal of a second one of the beta MOSFETs is coupled to the third node; or a gate terminal of the first one of the beta MOSFETs is coupled to the third node, and a gate terminal of the second one of the beta MOSFETs is coupled to the second node.
20. The method of claim 18, wherein the forming metallization segments and interconnection structures further electrically couples: the first capacitor and the first resistor of the first filter to each other at a second node and in series between (1) the first or second reference voltage rails and (2) the first node; the second capacitor and the second resistor of the second filter to each other at a third node and in series between the first and second reference voltage rails; and in accordance with either a set A of circumstances or a set B of circumstances; the set A of circumstances being a gate terminal of a first one of the beta MOSFETs to the second node and a gate terminal of a second one of the beta MOSFETs to the third node; and the set B of circumstances being a gate terminal of the first one of the beta MOSFETs to the third node and a gate terminal of the second one of the beta MOSFETs to the second node.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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