DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20200219446) in the view of Kwon (US 20230290305).
Regarding claim 1: Yoshida teaches a pixel circuit (Fig. 4 and paragraph [0053] teach a pixel circuit 11) comprising: a light-emitting element; a first switching element configured to control a driving current flowing through the light-emitting element (Fig. 4 and paragraph [0053-0065] teach a light-emitting element OLED, a first switching element M1 configured to control a driving current flowing through the OLED) and including an upper gate electrode, a lower gate electrode, and a semiconductor layer between the upper gate electrode and the lower gate electrode in a cross-sectional view of the pixel circuit (Fig. 1 and paragraph [0039-0040] teach an upper gate electrode 6, lower gate electrode 2, and a semiconductor layer 4 in between the gate electrodes); a second switching element electrically connected to the lower gate electrode and configured to transmit a data signal to the lower gate electrode based on a data control signal; and a storage capacitor including a first electrode electrically connected to the lower gate electrode (Fig. 4 and paragraph [0039-0040, 0053-0065] teach a second switching element M2 electrically connected to the lower gate electrode and configured to transmit a data signal to the lower gate electrode based on a data control signal Vdata; and a storage capacitor Cst including a first electrode electrically connected to the lower gate electrode).
Yoshida does not explicitly disclose a second electrode of the capacitor electrically connected to one of source-drain electrodes of the first switching element.
However, Kwon teaches a second electrode of the capacitor electrically connected to one of source-drain electrodes of the first switching element (Fig. 2 and paragraph [0091-0106] teach a second electrode of the capacitor Cst connected to source electrode of the first switching element T1). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Yoshida’s invention by including above teachings of Kwon, because connecting a storage capacitor as shown by Kwon and using pixel circuit structure of Kwon, allows the pixel circuit to perform optimally to achieve desirable image quality, which is very well-known and widely used method in art. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claims 2 & 15: Yoshida teaches wherein the first switching element is further configured to turn on or off based on an emission control signal transmitted through the upper gate electrode (Fig. 4 and paragraph [0039-0040, 0053-0065] teach the first switching element M1 is further configured to turn on or off based on an emission control signal as claimed Ej).
Regarding claims 3 & 16: Yoshida teaches wherein a magnitude of the driving current corresponds to the data signal transmitted through the lower gate electrode (Fig. 4 and paragraph [0039-0040, 0053-0065] teach wherein a magnitude of the driving current corresponds to the data signal Vdata transmitted through the lower gate electrode of M1).
Regarding claim 4: Combination of Yoshida and Kwon teach further comprising a third switching element electrically connected between the first electrode and a reference voltage line configured to transmit a reference voltage (Kwon in Fig. 2 and paragraph [0091-0106] teach a third switching element T4 electrically connected between the first electrode of capacitor CST and a reference voltage line Vref). See claim 1 rejection for combination reasoning of Yoshida and Kwon, same rationale applies here.
Regarding claim 5: Combination of Yoshida and Kwon teach wherein the light-emitting element includes an anode electrode electrically connected to the first switching element (Yoshida in Fig. 4 and paragraph [0039-0040, 0053-0065] teach the light-emitting element OLED includes an anode electrode connected to the first switching element M1), and the pixel circuit further comprises a fourth switching element electrically connected between the anode electrode and an initialization voltage line configured to transmit an initialization voltage (Kwon in Fig. 2 and paragraph [0091-0106] teach a fourth switching element T7 electrically connected between the anode electrode of OLED and an initialization voltage line Vint). See claim 1 rejection for combination reasoning of Yoshida and Kwon, same rationale applies here.
Regarding claims 6 & 17: Combination of Yoshida and Kwon teach wherein the light-emitting element includes an anode electrode electrically connected to the first switching element (Yoshida in Fig. 4 and paragraph [0039-0040, 0053-0065] teach the light-emitting element OLED includes an anode electrode connected to the first switching element M1), and the pixel circuit further comprises a fifth switching element electrically connected between the anode electrode and the first switching element (Kwon in Fig. 2 and paragraph [0091-0106] teach a fifth switching element T6 electrically connected between the anode electrode of OLED and the first switching element T1). See claim 1 rejection for combination reasoning of Yoshida and Kwon, same rationale applies here.
Regarding claim 7: Yoshida teaches wherein a semiconductor layer of the first switching element includes an oxide semiconductor (Fig. 1 and paragraph [0039-0040] teach an oxide semiconductor).
Regarding claim 8: Combination of Yoshida and Kwon teach wherein a semiconductor layer of the fifth switching element includes low-temperature polysilicon (Kwon in Fig. 2 and paragraph [0144] teach a semiconductor layer for transistors including fifth transistor T6 can a polysilicon. Yoshida in paragraph [0040] teach a semiconductor layer for transistors utilized in the pixel circuit includes low-temperature polysilicon. Therefore, it is very well-known in the art for transistor in pixel circuits to comprising a semiconductor layer including low-temperature polysilicon to achieve desired transistor properties). See claim 1 rejection for combination reasoning of Yoshida and Kwon, same rationale applies here.
Regarding claim 14: Yoshida teaches a display device (Fig. 3 and paragraph [0045] teach a display device) comprising: a pixel circuit including a light-emitting element configured to emit light according to a data signal and a gate control signal (Fig. 4 and paragraph [0053-0065] teach a pixel circuit 11 including a light-emitting element OLED to emit light based on a data signal Vdata and a gate control signal Ej); a gate driver configured to generate the gate control signal; a data driver configured to generate the data signal; and a controller configured to control the gate driver and the data driver (Fig. 3 and paragraph [0045-0052] teach a gate driver 60 to generate the gate control signal E, data driver 30 configured to generate the data signal; and a controller 20 configured to control the gate and data drivers), wherein the pixel circuit includes: a first switching element configured to control a driving current flowing through the light-emitting element (Fig. 4 and paragraph [0053-0065] teach the pixel circuit 11 includes a light-emitting element OLED, a first switching element M1 configured to control a driving current flowing through the OLED) and including an upper gate electrode, a lower gate electrode, and a semiconductor layer between the upper gate electrode and the lower gate electrode in a cross-sectional view of the pixel circuit (Fig. 1 and paragraph [0039-0040] teach an upper gate electrode 6, lower gate electrode 2, and a semiconductor layer 4 in between the gate electrodes); a second switching element electrically connected to the lower gate electrode and configured to transmit the data signal to the lower gate electrode based on a data control signal; and a storage capacitor including a first electrode electrically connected to the lower gate electrode (Fig. 4 and paragraph [0039-0040, 0053-0065] teach a second switching element M2 electrically connected to the lower gate electrode and configured to transmit a data signal to the lower gate electrode based on a data control signal Vdata; and a storage capacitor Cst including a first electrode electrically connected to the lower gate electrode).
Yoshida does not explicitly disclose a second electrode of the capacitor electrically connected to one of source-drain electrodes of the first switching element.
However, Kwon teaches a second electrode of the capacitor electrically connected to one of source-drain electrodes of the first switching element (Fig. 2 and paragraph [0091-0106] teach a second electrode of the capacitor Cst connected to source electrode of the first switching element T1). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Yoshida’s invention by including above teachings of Kwon, because connecting a storage capacitor as shown by Kwon and using pixel circuit structure of Kwon, allows the pixel circuit to perform optimally to achieve desirable image quality, which is very well-known and widely used method in art. The rationale would have been to use a known method or technique to achieve predictable results.
Claims 9, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20200219446), in the view of Kwon (US 20230290305), and further in the view of Kim (US 20230186851).
Regarding claims 9 & 18: Combination of Yoshida and Kwon do not explicitly disclose wherein the first electrode is a portion of the lower gate electrode.
However, Kim teaches wherein the first electrode of a capacitor is a portion of a gate electrode (Figs. 3, 8 and paragraph [0184] teach the first electrode of a capacitor Cst is a portion of a gate electrode GE1). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Yoshida and Kwon by including above teachings of Kim, because utilizing a gate electrode as a capacitor electrode is very well-known and widely used in the art, because it eliminates the need to placing another electrode during manufacturing process and keeping the design compact while providing the similar results, as taught by Kim. Similarly, the lower gate electrode of Kwon can be designed to use as the first electrode of capacitor. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 13: Combination of Yoshida, Kwon, and Kim teach wherein a first distance between an upper surface of the semiconductor layer of the first switching element and the upper gate electrode is less than a second distance between a lower surface of the semiconductor layer of the first switching element and the lower gate electrode (Kim in Fig. 8 and paragraph [0177] teach a first distance TS2 between an upper surface of the semiconductor layer ACT1 or SCP1 and the upper gate electrode GE1_1 is less than a second distance TS1 between a lower surface of the SPC1 and the lower gate electrode GE1_2). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Yoshida and Kwon by including above teachings of Kim, because larger distance allows the lower gate electrode to perform auxiliary functions optimally without any interference, as taught by Kim. The rationale would have been to use a known method or technique to achieve predictable results.
Claims 10, 11-12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20200219446), in the view of Kwon (US 20230290305), in the view of Kim (US 20230186851), and further in the view of Yuan (US 20220302244).
Regarding claims 10 & 19: Combination of Yoshida, Kwon, and Kim do not explicitly disclose wherein the second electrode is a portion of a semiconductor layer of the fifth switching element.
However, Yuan teaches wherein the second electrode is a portion of a semiconductor layer of the switching element (Fig. 6B-C & 9A and paragraph [0132, 0181] the second electrode Ca of the capacitor is a portion of a semiconductor layer of a switching element or transistor). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Yoshida, Kwon, and Kim, by including above teachings of Yuan, because utilizing such structure of transistors and capacitor within a pixel circuit is very well-known and widely used in the art, because of it’s compact design by utilizing same electrode for different functions while achieving similar desired results. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 11: Combination of Yoshida, Kwon, Kim, and Yuan wherein a portion of the lower gate electrode and a portion of the semiconductor layer of the fifth switching element overlap in a plan view of the pixel circuit (Yuan in Fig. 6B-C & 9A and paragraph [0132, 0181] the semiconductor layer 504 making capacitor electrode Ca, and a portion of the gate electrodes of various transistors such as 180, T2g overlap). See claim 10 rejection for combination reasoning of Yoshida, Kwon, Kim, and Yuan, same rationale applies here.
Regarding claim 12: Combination of Yoshida, Kwon, Kim, and Jung wherein the portion of the semiconductor layer of the fifth switching element is electrically connected to the one of the source-drain electrodes of the first switching element, and another one of the source-drain electrodes of the first switching element is electrically connected to a power voltage line transmitting a power voltage (Kwon in Fig. 2 and paragraph [0091-0106] teach wherein the portion of the semiconductor layer of the fifth switching element T6 electrically connected to the one or the source-drain electrodes of the first switching element T1, and another one of the source-drain electrodes of the first switching element T1 is electrically connected to a power voltage line transmitting a power voltage ELVDD). See claim 1 rejection for combination reasoning of Yoshida and Kwon, same rationale applies here.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20200219446), in the view of Kwon (US 20230290305), and further in the view of Yuan (US 20220302244).
Regarding claim 20: Yoshida teaches a display device which operates based on the data signals and/or the control signals (Fig. 3 and paragraph [0045] teach a display device), wherein the display device comprising: a pixel circuit including a light-emitting element configured to emit light according to a data signal and a gate control signal (Fig. 4 and paragraph [0053-0065] teach a pixel circuit 11 including a light-emitting element OLED to emit light based on a data signal Vdata and a gate control signal Ej); a gate driver configured to generate the gate control signal; a data driver configured to generate the data signal; and a controller configured to control the gate driver and the data driver (Fig. 3 and paragraph [0045-0052] teach a gate driver 60 to generate the gate control signal E, data driver 30 configured to generate the data signal; and a controller 20 configured to control the gate and data drivers), wherein the pixel circuit includes: a first switching element configured to control a driving current flowing through the light-emitting element (Fig. 4 and paragraph [0053-0065] teach the pixel circuit 11 includes a light-emitting element OLED, a first switching element M1 configured to control a driving current flowing through the OLED) and including an upper gate electrode, a lower gate electrode, and a semiconductor layer between the upper gate electrode and the lower gate electrode in a cross-sectional view of the pixel circuit (Fig. 1 and paragraph [0039-0040] teach an upper gate electrode 6, lower gate electrode 2, and a semiconductor layer 4 in between the gate electrodes); a second switching element electrically connected to the lower gate electrode and configured to transmit the data signal to the lower gate electrode based on a data control signal; and a storage capacitor including a first electrode electrically connected to the lower gate electrode (Fig. 4 and paragraph [0039-0040, 0053-0065] teach a second switching element M2 electrically connected to the lower gate electrode and configured to transmit a data signal to the lower gate electrode based on a data control signal Vdata; and a storage capacitor Cst including a first electrode electrically connected to the lower gate electrode).
Yoshida does not explicitly disclose a second electrode of the capacitor electrically connected to one of source-drain electrodes of the first switching element.
However, Kwon teaches a second electrode of the capacitor electrically connected to one of source-drain electrodes of the first switching element (Fig. 2 and paragraph [0091-0106] teach a second electrode of the capacitor Cst connected to source electrode of the first switching element T1). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Yoshida’s invention by including above teachings of Kwon, because connecting a storage capacitor as shown by Kwon and using pixel circuit structure of Kwon, allows the pixel circuit to perform optimally to achieve desirable image quality, which is very well-known and widely used method in art. The rationale would have been to use a known method or technique to achieve predictable results.
Combination of Yoshida and Kwon do not explicitly disclose an electronic device comprising: a memory which stores data information; a processor which generates data signals and/or control signals based on the data information.
However, Yuan teaches an electronic device comprising: a memory which stores data information; a processor which generates data signals and/or control signals based on the data information (Fig. 1 A and paragraph [0066-0069] a memory 122 and a processor 121 in a display device performing as claimed). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Yoshida, and Kwon, by including above teachings of Yuan, because utilizing a memory and a processor within an electronic display device is very well-known and widely used in the art in order to optimally control the functions of different drivers and circuits within the display, as taught by Yuan. The rationale would have been to use a known method or technique to achieve predictable results.
Conclusion
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/AMIT CHATLY/Primary Examiner, Art Unit 2624