DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2019/0147799; hereinafter Kim ‘799) , in view of Pyon et al (US 2016/0322449; hereinafter Pyon).
• Regarding claim 1, Kim ‘799 discloses a display device (figure 1), comprising:
a light emitting diode (element OLED in figure 2);
a first transistor configured to supply a driving current to the light emitting diode (element DT in figure 2 and ¶ 54);
a data line configured to transmit a data voltage (element DLk in figure 2 and ¶ 52);
a second transistor connected between the data line and a first electrode of the first transistor (element ST2 in figure 2 and ¶ 59);
an initialization voltage line configured to transmit an initialization voltage (Vint in figure 2 and ¶ 57);
a seventh transistor connected between the initialization voltage line and an anode of the light emitting diode (element ST1 in figure 2 and ¶ 57); and
a scan line configured to transmit a scan signal (element SPLj in figure 2 and ¶ 59).
However, Kim ‘799 fails to disclose the additional details of the display device.
In the same field of endeavor, Pyon discloses where the scan line being connected to a gate electrode of the second transistor and overlapping at least a portion of the initialization voltage line (note the relationship between elements 151 and 192 in figures 3 and 4 and ¶ 91).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799 according to the teachings of Pyon, for the purpose of maximizing storage capacitance in a high-resolution display structure (¶ 9).
• Regarding claims 2 and 3, Kim ‘799, in view of Pyon, discloses everything claimed, as applied to claim 1. Additionally, Kim ‘799 discloses where:
Claim 2: the data line extends in a first direction (element DLk in figure 2; see also figure 3 of Pyon), and
the scan line and the initialization voltage line extend in a second direction crossing the first direction (element SPLj and Vint in figure 2; see also figure 3 of Pyon).
However, Kim ‘799 fails to disclose the additional details of the display device.
In the same field of endeavor, Pyon discloses where:
Claim 3: the display device further comprises:
a substrate (element 110 in figure 5);
a first insulating layer disposed between the substrate and the scan line (element 120 in figure 5 and ¶ 125; where element 155b in figure 5 and ¶ 126 is part of element 151 in figure 2); and
a second insulating layer disposed between the scan line and the initialization voltage line (at least one of elements 160 and 180 in figure 6 and ¶s 127 and 135).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799 according to the teachings of Pyon, for the purpose of maximizing storage capacitance in a high-resolution display structure (¶ 9).
Claims 4 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘799, in view of Pyon, and further in view of Kim et al (US 2018/0006105; hereinafter Kim ‘105).
• Regarding claims 4 and 9-12, Kim ‘799, in view of Pyon, discloses everything claimed, as applied to claim 1. Additionally, Kim ‘799 discloses where:
Claim 4: the display device further comprises:
a third transistor connected between the gate electrode of the first transistor and a second electrode of the first transistor (element ST4 in figure 2 and ¶ 63).
Claim 9: the display device further comprises:
a driving voltage line configured to transmit a driving voltage (ELVDD in figure 2);
a fifth transistor connected between the driving voltage line and the first electrode of the first transistor (element ST5 in figure 2 and ¶ 65);
a sixth transistor connected between the second electrode of the first transistor and the anode of the light emitting diode (element ST6 in figure 2 and ¶ 67); and
a storage capacitor connected between the driving voltage line and the gate electrode of the first transistor (element Cst in figure 2 and ¶ 74).
Claim 11: each of the first transistor, the second transistor, and the seventh transistor include a polycrystalline semiconductor layer (elements DT, ST1, ST2, ST5, and ST6 in figure 6 and ¶ 79), and
each of the third transistor and the fourth transistor include an oxide semiconductor layer (elements ST3 and ST4 in figure 6 and ¶ 79).
Claim 12: each of the fifth transistor and the sixth transistor include a polycrystalline semiconductor layer (elements DT, ST1, ST2, ST5, and ST6 in figure 6 and ¶ 79).
However, Kim ‘799, in view of Pyon, fails to disclose the additional details of the display device.
In the same field of endeavor, Kim ‘105 discloses where:
Claim 4: the display device further comprises:
a third transistor connected between the gate electrode of the first transistor and a second electrode of the first transistor (element T4 in figure 5 and ¶ 142);
another initialization voltage line configured to transmit an initialization voltage different from the initialization voltage transmitted by the initialization voltage line (Vint1 in figure 5); and
a fourth transistor connected between the another initialization voltage line and the gate electrode of the first transistor (element T3 in figure 5 and ¶ 141).
Claim 10: the display device further comprises:
an initialization control line configured to transmit an initialization control signal and connected to a gate electrode of the fourth transistor (Si-1 in figure 5), and
the another initialization voltage line and the initialization control line are disposed in a same layer (¶s 190 and 191).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799, as modified by Pyon, according to the teachings of Kim ‘105, for the purpose of providing a display device in which a dead space may be minimized (¶ 8).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘799, in view of Pyon and Kim ‘105, and further in view of Kim (US 2008/0203931; hereinafter Kim ‘931).
• Regarding claim 13, Kim ‘799, in view of Pyon and Kim ‘105, discloses everything claimed, as applied to claim 4. However, Kim ‘799 fails to disclose the additional details of the display device.
In the same field of endeavor, Pyon discloses where:
Claim 13: the display device further comprises:
a substrate (element 110 in figure 7 and ¶ 124);
a first insulating layer disposed between the substrate and the scan line (element 120 in figure 7 and ¶ 124);
a second insulating layer disposed between the scan line and the initialization voltage line (element 140 in figure 7 and ¶ 126); and
a fourth insulating layer disposed between the second insulating layer and the another initialization voltage line (element 160 in figure 7 and ¶s 127 and 128).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799 according to the teachings of Pyon, for the purpose of maximizing storage capacitance in a high-resolution display structure (¶ 9). However, Pyon and Kim ‘105 also fail to disclose the additional details of the display device.
In the same field of endeavor, Kim ‘931 discloses where:
Claim 13: the display device further comprises:
a substrate (element 210 in figures 8 and 9);
a second insulating layer disposed between the scan line and the initialization voltage line (element 214 in figures 8 and 9 and ¶ 86);
a third insulating layer disposed between the initialization voltage line and the another initialization voltage line (element 218 in figures 8 and 9 and ¶ 86); and
a fourth insulating layer disposed between the second insulating layer and the another initialization voltage line (element 222 in figures 8 and 9 and ¶ 96).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799, as modified by Pyon and Kim ‘105, according to the teachings of Kim ‘931, for the purpose of enabling an image of a predetermined brightness to be displayed (¶ 97).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘799, in view of Pyon, Kim ‘105, and Kim ‘931, and further in view of Kang et al (US 2019/0088209; hereinafter Kang).
• Regarding claims 14 and 15, Kim ‘799, in view of Pyon, Kim ‘105, and Kim ‘931, discloses everything claimed, as applied to claim 13. However, Kim ‘799, in view of Pyon, Kim ‘105, and Kim ‘931, fails to disclose the additional details of the display device.
In the same field of endeavor, Kang discloses where:
Claim 14: each of the first transistor, second transistor, and the seventh transistor includes a semiconductor layer disposed between the substrate and the first insulating layer (note the relationship between elements 100, 710, and 750 in figure 5 and ¶s 88, 90, 92, 93, and 99), and
each of the third transistor and the fourth transistor includes a semiconductor layer disposed between the third insulating layer and the fourth insulating layer (note the relationship between elements 410, 730, and 740 in figure 5 and ¶s 123 and 143).
Claim 15: the gate electrode of the first transistor, the gate electrode of the second transistor, and a gate electrode of the seventh transistor are disposed between the first insulating layer and the second insulating layer (note the relationship between elements 210, 710, and 720 in figure 5 and ¶ 101), and
a gate electrode of the third transistor and a gate electrode of the fourth transistor are disposed on the fourth insulating layer (note the relationship between elements 320, 720, and 730 in figure 5 and ¶s 115-118, in view of “[t]” in ¶ 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799, as modified by Pyon, Kim ‘105, and Kim ‘931, according to the teachings of Kang for the purpose of preventing a voltage of a gate electrode of a transistor from being excessively reduced due to a kickback (¶ 7).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘799, in view of Pyon, Kim ‘105, Kim ‘931, and Kang, and further in view of Kim et al (US 2018/0350891; hereinafter Kim ‘891).
Regarding claim 20, Kim ‘799, in view of Pyon, Kim ‘105, Kim ‘931, and Kang, discloses everything claimed, as applied to claim 14. However, Kim ‘799, in view of Pyon, Kim ‘105, Kim ‘931, and Kang, fails to disclose the additional details of the display device.
In the same field of endeavor, Kim ‘891 discloses where:
Claim 20: the display device further comprises:
a light blocking layer overlapping the semiconductor layer of the third transistor (element 70 in figures 4-6 and ¶ 147), and
the light blocking layer and the initialization voltage line are disposed in a same layer (¶ 147).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim ‘799, as modified by Pyon, Kim ‘105, Kim ‘931, and Kang, according to the teachings of Kim ‘891, for the purpose of minimizing light-generated leakage current in an oxide semiconductor (¶s 7 and 8).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4, 5, 7-9, and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 15, and 19 of U.S. Patent No. 11,455,943 (resulting from parent application 17/187,996). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). Note the following table.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 15 of U.S. Patent No. 11,455,943, in view of Kim ‘105.
• Regarding claim 10, US 11,455,943 claims everything in claims 3 and 15 except the additional details of the display device.
In the same field of endeavor, Kim ‘105 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 19 of U.S. Patent No. 11,455,943, in view of Kim ‘799.
• Regarding claim 12, US 11,455,943 claims everything in claims 15 and 19 except the additional details of the display device.
In the same field of endeavor, Kim ‘799 teaches the additional details of the display device, as previously indicated in this Office action.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 11,455,943 according to the teachings of Kim ‘799, for the purpose of minimizing a decrease in display quality that may be caused by a kickback-induced voltage drop (¶ 17).
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 15 of U.S. Patent No. 11,455,943, in view of Kim ‘105.
• Regarding claim 13, US 11,455,943 claims everything in claims 3 and 15 except the additional details of the display device.
In the same field of endeavor, Kim ‘105 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claims 14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 15 of U.S. Patent No. 11,455,943, in view of Kim ‘105, and further in view of Kang.
• Regarding claims 14 and 15, US 11,455,943, in view of Kim ‘105, claims everything in claims 3 and 15 except the additional details of the display device.
In the same field of endeavor, Kang teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 15 of U.S. Patent No. 11,455,943, in view of Kim ‘105 and Kang, and further in view of Kim ‘891.
• Regarding claim 20, US 11,455,943, in view of Kim ‘105 and Kang, claims everything in claims 3 and 15 except the additional details of the display device.
In the same field of endeavor, Kim ‘891 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
US 19/247,682
US 11,455,943 (resulting from 17/187,996)
1. A display device, comprising:
a light emitting diode;
a first transistor configured to supply a driving current to the light emitting diode;
a data line configured to transmit a data voltage;
a second transistor connected between the data line and a first electrode of the first transistor;
an initialization voltage line configured to transmit an initialization voltage;
a seventh transistor connected between the initialization voltage line and an anode of the light emitting diode; and
a scan line configured to transmit a scan signal,
the scan line being connected to a gate electrode of the second transistor and overlapping at least a portion of the initialization voltage line.
1. (Rearranged) A display device comprising:
a light emitting diode (LED) connected to the driving transistor and the first electrode of the seventh transistor.
a substrate;
a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a driving transistor and a channel, a first electrode, and a second electrode of a seventh transistor;
3. …a data line overlapping the first initialization voltage line and the second initialization voltage line; and
a second transistor connected to the scan line and the data line.
1. …a gate electrode of the driving transistor overlapping the channel of the driving transistor;
a gate electrode of the seventh transistor overlapping the channel of the seventh transistor;
an oxide semiconductor layer on the substrate, the oxide semiconductor layer including a channel, a first electrode, and a second electrode of a fourth transistor;
a gate electrode of the fourth transistor overlapping the channel of the fourth transistor;
a first initialization voltage line connected to the first electrode of the fourth transistor,
…a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a driving transistor and a channel, a first electrode, and a second electrode of a seventh transistor; …
…wherein the first initialization voltage line and the gate electrode of the fourth transistor are positioned on a same layer,
wherein the second electrode of the fourth transistor is connected to the gate electrode of the driving transistor;
a second initialization voltage line connected to the second electrode of the seventh transistor,
wherein the second initialization voltage line and the first initialization voltage line are positioned on different layers from each other; and
a light emitting diode (LED) connected to the driving transistor and the first electrode of the seventh transistor.
3. The display device of claim 2, further comprising:
a scan line overlapping the first initialization voltage line and the second initialization voltage line;
a data line overlapping the first initialization voltage line and the second initialization voltage line; and
a second transistor connected to the scan line and the data line.
4. The display device of claim 1, further comprising:
a third transistor connected between the gate electrode of the first transistor and a second electrode of the first transistor;
another initialization voltage line configured to transmit an initialization voltage different from the initialization voltage transmitted by the initialization voltage line; and
a fourth transistor connected between the another initialization voltage line and the gate electrode of the first transistor.
15. A display device comprising: …
a third transistor connected between a second electrode of the driving transistor connected to the light emitting, diode (LED) and a gate electrode of the driving transistor;
a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied;
5. The display device of claim 4, wherein
the scan line overlaps at least a portion of the another initialization voltage line.
3. The display device of claim 2, further comprising:
a scan line overlapping the first initialization voltage line and the second initialization voltage line; …
7. The display device of claim 4, wherein
the initialization voltage line and the another initialization voltage line are disposed in different layers from each other.
1. A display device comprising: …
wherein the second initialization voltage line and the first initialization voltage line are positioned on different layers from each other; and …
8. The display device of claim 7, wherein
the initialization voltage line overlaps at least a portion of the another initialization voltage line.
2. The display device of claim 1, wherein
the first initialization voltage line overlaps the second initialization voltage line.
9. The display device of claim 4, further comprising:
a driving voltage line configured to transmit a driving voltage;
a fifth transistor connected between the driving voltage line and the first electrode of the first transistor;
a sixth transistor connected between the second electrode of the first transistor and the anode of the light emitting diode; and
a storage capacitor connected between the driving voltage line and the gate electrode of the first transistor.
15. A display device comprising:
a light emitting diode (LED) connected between a driving voltage line for applying a driving voltage to an anode of the light emitting diode and a common voltage line for applying a common voltage to a cathode of the light emitting diode;
a driving transistor connected between the driving voltage line and the anode of the light emitting diode (LED) and configured to supply a driving current to the light emitting diode;
a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied;
a third transistor connected between a second electrode of the driving transistor connected to the light emitting, diode (LED) and a gate electrode of the driving transistor;
a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied;
a seventh transistor connected between the anode of the light emitting diode (LED) and a second initialization voltage line to which a second initialization voltage is applied; …
19. The display device of claim 18, further comprising:
a fifth transistor connected between the driving voltage line and the first electrode of driving transistor; and
a sixth transistor connected between the first electrode of the driving transistor and the light emitting diode (LED).
15. …a storage capacitor connected between the driving voltage line and the gate electrode of the driving transistor,
wherein each of the driving transistor and the second transistor includes a polycrystalline semiconductor layer, and
wherein each of the third transistor and the fourth transistor includes an oxide semiconductor layer; and
a scan line connected to the second transistor and receiving a scan signal,
wherein the scan line overlaps the first initialization voltage line and the second initialization voltage line.
11. The display device of claim 4, wherein
each of the first transistor, the second transistor, and the seventh transistor include a polycrystalline semiconductor layer, and
each of the third transistor and the fourth transistor include an oxide semiconductor layer.
15. A display device comprising: …
wherein each of the driving transistor and the second transistor includes a polycrystalline semiconductor layer, and …
1. A display device comprising: …
a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a driving transistor and a channel, a first electrode, and a second electrode of a seventh transistor; …
15. …wherein each of the third transistor and the fourth transistor includes an oxide semiconductor layer; and …
Claims 1, 4, 5, 7-10, and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 11, 17, 22-24, and 26 of U.S. Patent No. 11,776,466 (resulting from parent application 17/935,372). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). Note the following table.
Claims 2 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,776,466, in view of Kim ‘799.
• Regarding claims 2 and 11, US 11,776,466 claims everything in claim 3 except the additional details of the display device.
In the same field of endeavor, Kim ‘799 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,776,466, in view of Pyon.
• Regarding claim 3, US 11,776,466 claims everything in claim 3 except the additional details of the display device.
In the same field of endeavor, Pyon teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 11 of U.S. Patent No. 11,776,466, in view of Kim ‘931.
• Regarding claim 13, US 11,776,466 claims everything in claims 3 and 11 except the additional details of the display device.
In the same field of endeavor, Kim ‘931 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claims 14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 11 of U.S. Patent No. 11,776,466, in view of Kim ‘931 and Kang.
• Regarding claim 20, US 11,776,466, in view of Kim ‘931, claims everything in claims 3 and 11 except the additional details of the display device.
In the same field of endeavor, Kang teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 11 of U.S. Patent No. 11,776,466, in view of Kim ‘931 and Kang, and further in view of Kim ‘891.
• Regarding claim 20, US 11,776,466, in view of Kim ‘931 and Kang, claims everything in claims 3 and 11 except the additional details of the display device.
In the same field of endeavor, Kim ‘891 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
US 19/247,682
US 11,776,466 (resulting from 17/935,372)
1. A display device, comprising:
a light emitting diode;
a first transistor configured to supply a driving current to the light emitting diode;
a data line configured to transmit a data voltage;
a second transistor connected between the data line and a first electrode of the first transistor;
an initialization voltage line configured to transmit an initialization voltage;
a seventh transistor connected between the initialization voltage line and an anode of the light emitting diode; and
a scan line configured to transmit a scan signal,
the scan line being connected to a gate electrode of the second transistor and overlapping at least a portion of the initialization voltage line.
1. A display device comprising:
See claim 1 below
a substrate;
a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first region, and a second region of a driving transistor, and a channel, a first region, and a second region of a seventh transistor;
See claim 3 below
See claim 3 below
a gate electrode of the driving transistor overlapping the channel of the driving transistor;
a gate electrode of the seventh transistor overlapping the channel of the seventh transistor;
an oxide semiconductor layer on the substrate, the oxide semiconductor layer including a channel, a first region, and a second region of a fourth transistor;
a gate electrode of the fourth transistor overlapping the channel of the fourth transistor;
a first initialization voltage line connected to the fourth transistor,
wherein the first initialization voltage line and the gate electrode of the fourth transistor are positioned on a same layer,
wherein the fourth transistor is connected to the gate electrode of the driving transistor;
a second initialization voltage line connected to the seventh transistor,
See claim 1 above
wherein the second initialization voltage line and the first initialization voltage line are positioned on different layers from each other; and
a light emitting diode (LED) connected to the driving transistor and the seventh transistor.
3. The display device of claim 1, further comprising:
a scan line overlapping at least one of the first initialization voltage line and the second initialization voltage line;
a data line overlapping at least one of the first initialization voltage line and the second initialization voltage line; and
a second transistor connected to the scan line and the data line.
4. The display device of claim 1, further comprising:
a third transistor connected between the gate electrode of the first transistor and a second electrode of the first transistor;
another initialization voltage line configured to transmit an initialization voltage different from the initialization voltage transmitted by the initialization voltage line; and
a fourth transistor connected between the another initialization voltage line and the gate electrode of the first transistor.
11. The display device of claim 1, further comprising:
a first storage electrode overlapping the gate electrode of the driving transistor,
wherein the second initialization voltage line and the first storage electrode are on a same layer,
wherein the oxide semiconductor layer further includes a channel, a first region, and a second region of a third transistor, and
wherein the channel of the third transistor and the channel of the fourth transistor are positioned on a same layer.
5. The display device of claim 4, wherein
the scan line overlaps at least a portion of the another initialization voltage line.
3. The display device of claim 1, further comprising:
a scan line overlapping at least one of the first initialization voltage line and the second initialization voltage line; …
7. The display device of claim 4, wherein
the initialization voltage line and the another initialization voltage line are disposed in different layers from each other.
1. A display device comprising: …
wherein the second initialization voltage line and the first initialization voltage line are positioned on different layers from each other; and …
8. The display device of claim 7, wherein
the initialization voltage line overlaps at least a portion of the another initialization voltage line.
2. The display device of claim 1, wherein
the first initialization voltage line overlaps the second initialization voltage line.
9. The display device of claim 4, further comprising:
a driving voltage line configured to transmit a driving voltage;
a fifth transistor connected between the driving voltage line and the first electrode of the first transistor;
a sixth transistor connected between the second electrode of the first transistor and the anode of the light emitting diode; and
a storage capacitor connected between the driving voltage line and the gate electrode of the first transistor.
17. A display device comprising:
a light emitting diode (LED) connected between a driving voltage line for applying a driving voltage to an anode of the light emitting diode and a common voltage line for applying a common voltage to a cathode of the light emitting diode;
See claim 22 below
See claim 22 below
a driving transistor connected between the driving voltage line and the anode of the light emitting diode (LED) and configured to supply a driving current to the light emitting diode;
a second transistor connected between a first region of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied;
a third transistor connected between a second region of the driving transistor connected to the light emitting diode (LED) and a gate electrode of the driving transistor;
a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied;
a seventh transistor connected between the anode of the light emitting diode (LED) and a second initialization voltage line to which a second initialization voltage is applied;
a storage capacitor connected between the driving voltage line and the gate electrode of the driving transistor,
wherein each of the driving transistor and the second transistor includes a polycrystalline semiconductor layer, and wherein each of the third transistor and the fourth transistor includes an oxide semiconductor layer; and
a scan line connected to the second transistor and receiving a scan signal,
wherein the scan line overlaps a portion of the second initialization voltage line.
22. The display device of claim 21, further comprising:
a fifth transistor connected between the driving voltage line and the first region of driving transistor; and
a sixth transistor connected between the first region of the driving transistor and the light emitting diode (LED).
10. The display device of claim 4, further comprising:
an initialization control line configured to transmit an initialization control signal and connected to a gate electrode of the fourth transistor,
wherein the another initialization voltage line and the initialization control line are disposed in a same layer.
24. The display device of claim 22, further comprising:
an inverted scan line connected to the third transistor and receiving an inverted scan signal;
an initialization control line connected to the fourth transistor and receiving an initialization control signal;
an emission control line connected to the fifth transistor and the sixth transistor and receiving an emission control signal; and
a bypass control line connected to the seventh transistor and receiving a bypass signal.
26. The display device of claim 17, wherein
the first initialization voltage line and the second initialization voltage line are disposed on different layers from each other.
12. The display device of claim 9, wherein
each of the fifth transistor and the sixth transistor include a polycrystalline semiconductor layer.
23. The display device of claim 22, wherein
each of the fifth transistor, the sixth transistor, and the seventh transistor includes a polycrystalline semiconductor layer.
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Claims 1, 3, 4, 11, 13-17, 19, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5-13, 15, and 16 of U.S. Patent No. 12,355,020 (resulting from parent application 18/458,526). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). Note the following table.
Claims 2, 9, and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,355,020, in view of Kim ‘799.
• Regarding claims 2, 9, and 12, US 12,355,020 claims everything in claim 3 except the additional details of the display device.
In the same field of endeavor, Kim ‘799 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,355,020, in view of Kim ‘105.
• Regarding claim 10, US 12,355,020, in view of Kim ‘931 and Kang, claims everything in claim 3 except the additional details of the display device.
In the same field of endeavor, Kim ‘105 teaches the additional details of the display device, as previously indicated in this Office action, and for the reasons previously indicated in this Office action.
US 19/247,682
US 12,355,020 (resulting from 18/458,526)
1. A display device, comprising:
a light emitting diode;
a first transistor configured to supply a driving current to the light emitting diode;
a data line configured to transmit a data voltage;
a second transistor connected between the data line and a first electrode of the first transistor;
an initialization voltage line configured to transmit an initialization voltage;
a seventh transistor connected between the initialization voltage line and an anode of the light emitting diode; and
a scan line configured to transmit a scan signal,
the scan line being connected to a gate electrode of the second transistor and overlapping at least a portion of the initialization voltage line.
1. (rearranged) A display device, comprising: …
…a light emitting diode including an anode, a cathode, and a light emitting layer; …
…a first transistor including a polycrystalline semiconductor layer;
See claim 3 below
a second transistor including a polycrystalline semiconductor layer and connected to the first transistor;
a third transistor including an oxide semiconductor layer and connected to the first transistor;
a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor,
wherein the fourth transistor is connected to a gate electrode of the first transistor;
a boost capacitor including a first electrode and a second electrode overlapping the first electrode,
wherein the first electrode is connected to the second transistor, and the second electrode is connected to at least one of the third transistor and the fourth transistor; …
…a first initialization voltage line connected to an electrode of the fourth transistor and transmitting a first initialization voltage; and
a second initialization voltage line connected to an electrode of the seventh transistor and transmitting a second initialization voltage different from the first initialization voltage, …
…a seventh transistor connected to the light emitting diode; …
wherein the first initialization voltage line and the second initialization voltage line are disposed on different layers from each other.
3. The display device of claim 2, further comprising:
a scan line overlapping the first initialization voltage line and the second initialization voltage line;
a data line overlapping the first initialization voltage line and the second initialization voltage line; and
a second transistor connected to the scan line and the data line.
3. The display device of claim 1, further comprising:
a substrate;
a first insulating layer disposed between the substrate and the scan line; and
a second insulating layer disposed between the scan line and the initialization voltage line.
5. The display device of claim 1, further comprising:
a substrate;
a first insulating layer disposed between the substrate and the first electrode;
a second insulating layer disposed between the first electrode and the second electrode;
a third insulating layer disposed between the second insulating layer and the second electrode; and
a fourth insulating layer disposed on the second electrode.
4. The display device of claim 1, further comprising:
a third transistor connected between the gate electrode of the first transistor and a second electrode of the first transistor;
another initialization voltage line configured to transmit an initialization voltage different from the initialization voltage transmitted by the initialization voltage line; and
a fourth transistor connected between the another initialization voltage line and the gate electrode of the first transistor.
1. A display device, comprising: …
a third transistor including an oxide semiconductor layer and connected to the first transistor; …
…a first initialization voltage line connected to an electrode of the fourth transistor and transmitting a first initialization voltage; and …
…a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor,
wherein the fourth transistor is connected to a gate electrode of the first transistor; …
9. The display device of claim 4, further comprising:
a driving voltage line configured to transmit a driving voltage;
a fifth transistor connected between the driving voltage line and the first electrode of the first transistor;
a sixth transistor connected between the second electrode of the first transistor and the anode of the light emitting diode; and
a storage capacitor connected between the driving voltage line and the gate electrode of the first transistor.
11. The display device of claim 1, further comprising:
a driving voltage line transmitting a driving voltage;
a fifth transistor connected between the driving voltage line and the first transistor; and
a sixth transistor connected between the first transistor and the light emitting diode and connected to the seventh transistor.
Kim ‘799, as previously indicated
11. The display device of claim 4, wherein
each of the first transistor, the second transistor, and the seventh transistor include a polycrystalline semiconductor layer, and
each of the third transistor and the fourth transistor include an oxide semiconductor layer.
1. A display device, comprising:
a first transistor including a polycrystalline semiconductor layer;
a second transistor including a polycrystalline semiconductor layer and connected to the first transistor; …
12. The display device of claim 11, wherein
each of the fifth transistor, the sixth transistor, and the seventh transistor includes a polycrystalline semiconductor layer.
…a third transistor including an oxide semiconductor layer and connected to the first transistor;
a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor,
12. The display device of claim 9, wherein
each of the fifth transistor and the sixth transistor include a polycrystalline semiconductor layer.
12. The display device of claim 11, wherein
each of the fifth transistor, the sixth transistor, and the seventh transistor includes a polycrystalline semiconductor layer.
13. The display device of claim 4, further comprising:
a substrate;
a first insulating layer disposed between the substrate and the scan line;
a second insulating layer disposed between the scan line and the initialization voltage line;
a third insulating layer disposed between the initialization voltage line and the another initialization voltage line; and
a fourth insulating layer disposed between the second insulating layer and the another initialization voltage line.
5. The display device of claim 1, further comprising:
a substrate;
a first insulating layer disposed between the substrate and the first electrode;
a second insulating layer disposed between the first electrode and the second electrode;
a third insulating layer disposed between the second insulating layer and the second electrode; and
a fourth insulating layer disposed on the second electrode.
14. The display device of claim 13, wherein
each of the first transistor, second transistor, and the seventh transistor includes a semiconductor layer disposed between the substrate and the first insulating layer, and
each of the third transistor and the fourth transistor includes a semiconductor layer disposed between the third insulating layer and the fourth insulating layer.
6. The display device of claim 5, wherein
the polycrystalline semiconductor layer of the first transistor and the polycrystalline semiconductor layer of the second transistor are disposed between the substrate and the first insulating layer.
7. The display device of claim 5, wherein
the oxide semiconductor layer of the third transistor and the oxide semiconductor layer of the fourth transistor are disposed between the third insulating layer and the fourth insulating layer.
15. The display device of claim 13, wherein
the gate electrode of the first transistor, the gate electrode of the second transistor, and a gate electrode of the seventh transistor are disposed between the first insulating layer and the second insulating layer, and
a gate electrode of the third transistor and a gate electrode of the fourth transistor are disposed on the fourth insulating layer.
8. The display device of claim 5, wherein
a gate electrode of the first transistor and a gate electrode of the second transistor are disposed between the first insulating layer and the second insulating layer.
9. The display device of claim 5, wherein
a gate electrode of the third transistor and a gate electrode of the fourth transistor are disposed on the fourth insulating layer.
16. The display device of claim 15, wherein
the another initialization voltage line and the gate electrode of the fourth transistor are disposed in a same layer.
10. The display device of claim 6, wherein
the first initialization voltage line and a gate electrode of the fourth transistor are disposed on a same layer.
17. The display device of claim 14, further comprising:
a fifth insulating layer disposed on the initialization voltage line; and
a connection electrode disposed on the fifth insulating layer and electrically connecting the initialization voltage line and the semiconductor layer of the fourth transistor.
15. A display device, comprising:
a first transistor including a polycrystalline semiconductor layer;
a second transistor including a polycrystalline semiconductor layer and connected to the first transistor;
a third transistor including an oxide semiconductor layer and connected to the first transistor;
a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor;
a boost capacitor including a first electrode and a second electrode overlapping the first electrode,
wherein the first electrode is connected to the second transistor, and the second electrode is connected to at least one of the third transistor and the fourth transistor;
a substrate;
a first insulating layer disposed between the substrate and the first electrode;
a second insulating layer disposed between the first electrode and the second electrode;
a third insulating layer disposed between the second insulating layer and the second electrode;
a fourth insulating layer disposed on the second electrode;
a first initialization voltage line connected to the fourth transistor and transmitting a first initialization voltage;
a fifth insulating layer disposed on the first initialization voltage line; and
a first connection electrode disposed on the fifth insulating layer and electrically connecting the first initialization voltage line and the oxide semiconductor layer of the fourth transistor.
19. The display device of claim 17, further comprising:
a connection electrode disposed on the fifth insulating layer and electrically connecting the semiconductor layer of the first transistor and the semiconductor layer of the third transistor.
16. The display device of claim 15, further comprising:
a second connection electrode disposed on the fifth insulating layer and electrically connecting the polycrystalline semiconductor layer of the first transistor and the oxide semiconductor layer of the third transistor.
20. The display device of claim 14, further comprising:
a light blocking layer overlapping the semiconductor layer of the third transistor,
wherein the light blocking layer and the initialization voltage line are disposed in a same layer.
13. The display device of claim 1, further comprising:
a light blocking layer overlapping the oxide semiconductor layer of the third transistor,
wherein the light blocking layer and the second initialization voltage line are disposed on a same layer.
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Allowable Subject Matter
Claims 6 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5, 7, 8, 16, 17, and 19 would be allowable if rewritten to overcome the Double Patenting rejection(s) set forth in this Office action or upon the filing of at least one proper Terminal Disclaimer cumulatively listing every US Patent and US Application forming the basis of the Double Patenting rejection(s) set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims. See MPEP §§ 804.02(II) and 804.02(IV).
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest:
a. In claim 5, where “the scan line overlaps at least a portion of the another initialization voltage line”, in combination with all the limitations in all the claims from which it depends.
b. In claim 6, where “the data line extends in a first direction, and the scan line and the another initialization voltage line extend in a second direction crossing the first direction”, in combination with all the limitations in all the claims from which it depends.
c. In claim 7, where “the initialization voltage line and the another initialization voltage line are disposed in different layers from each other”, in combination with all the limitations in all the claims from which it depends.
d. Claim 8 would be allowable based on its dependence from claim 7.
e. In claim 16, where “the another initialization voltage line and the gate electrode of the fourth transistor are disposed in a same layer”, in combination with all the limitations in all the claims from which it depends.
f. In claim 17, where “a fifth insulating layer disposed on the initialization voltage line; and a connection electrode disposed on the fifth insulating layer and electrically connecting the initialization voltage line and the semiconductor layer of the fourth transistor”, in combination with all the limitations in all the claims from which it depends.
g. In claim 18, where “the display device further comprises a connection electrode disposed on the fifth insulating layer and electrically connecting the initialization voltage line and the semiconductor layer of the seventh transistor”, in combination with all the limitations in all the claims from which it depends.
h. Claim 19 would be allowable based on its dependence from claim 17.
Closing Remarks/Comments
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622