DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . All the claims have been examined on the basis of the merit of the claims.
Priority
The present application claims foreign priority benefits from KR1020240084311 filed in Korea on 06/27/2024. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/20/2025 & 06/24/2025 are considered and attached.
Claim Interpretation
The claims are given broadest reasonable interpretations, MPEP 2111. The terms “connected to,” and “coupled to” are interpreted throughout this office action as an indirect electrical connection unless otherwise expressly recited as direct electrical connection. Transitional terms such as “comprising” are interpreted to be open ended inclusion, MPEP 2111.03. Terms marked in [] need grammatical corrections. No claim objections have been made for grammatical issues.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-9, 11-12 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO et al. (US-20220230581-A1, hereinafter as CHO) in view of KIM et al. (US-20220084472-A1, hereinafter as KIM).
In regard to claim 1, CHO a display device (referring to figs. 1, 3 and 7, a display device) comprising: a display panel including a pixel (display device comprising a display panel 100 having the pixel circuit as shown at fig. 7), wherein the pixel includes: a light emitting element including an anode connected to a first power line and a cathode (LED which includes anode and cathode, anode is connected to VDD); a first transistor connected between the cathode and a second power line (T17 connected between VSS and cathode of LED 30), wherein the first transistor operates based on a potential of a first node (N13); a second transistor connected between a second node and a data line (T11 between node N12 and data line D[j]), wherein the second transistor receives a first scan signal (S[i]); a first capacitor between the first node and the second node (Cst); a third transistor connected between a first electrode of the first transistor and the first node (T16 between N13 and T17), wherein the third transistor receives a second scan signal (P[i]); and a fourth transistor which initializes the second node in response to the second scan signal during an initialization period (T12 in response to the scan signa S[i] N11 as the initialized node, para 0149).
CHO does not disclose “a second capacitor connected between the second node and the first power line.”
KIM discloses a second capacitor connected between the second node and the first power line (fig. 1, C1 connected to between ELVDD and node N1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing of the application, to use KIM’s teachings of in CHO’s invention to reduce leakage currents of the transistors and display with uniform luminance, para 0100, KIM.
In regard to claim 20, CHO discloses an electronic device (fig. 6) comprising: a display panel including a pixel (display panel 100 including pixel PXij); a panel driver driving the display panel (data driver 120); a driving controller which controls a driving of the panel driver (signal controller 140); and a main processor which provides an image signal to the driving controller (not shown and labelled but para 0110, the signal controller 140 receives an image signal IS inputted from outside and provides image/video data signal DATA, fig.6 to data driver), wherein the pixel (referring to fig. 7) includes: a light emitting element (LED) including an anode (anode) connected to a first power line (VDD) and a cathode (cathode); a first transistor connected between the cathode and a second power line (T17 connected between VSS and cathode of LED 30), wherein the first transistor operates based on a potential of a first node (N13); a second transistor connected between a second node and a data line (T11 between node N12 and data line D[j]), wherein the second transistor receives a first scan signal (S[i]); a first capacitor between the first node and the second node (Cst); a third transistor connected between a first electrode of the first transistor and the first node (T16 between N13 and T17), wherein the third transistor receives a second scan signal (P[i]); and a fourth transistor which initializes the second node in response to the second scan signal during an initialization period (T12 in response to the scan signa S[i] N11 as the initialized node, para 0149).
CHO does not disclose “a second capacitor connected between the second node and the first power line.”
KIM discloses a second capacitor connected between the second node and the first power line (fig. 1, C1 connected to between ELVDD and node N1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing of the application, to use KIM’s teachings of in CHO’s invention to reduce leakage currents of the transistors and display with uniform luminance, para 0100, KIM.
In regard to claim 15, CHO discloses a display device (fig. 6) comprising: a display panel including a pixel (referring figs.6-7, display panel 10o with PXij), a first scan line(S[i]), a second scan line(p[i]), an emission control line(EM[i]), a first power line (VDD), a second power line(VSS), and a data line (D[j]); a first scan driving circuit connected to the first scan line (SL1 is connected to scan driver 110); a second scan driving circuit connected to the second scan line (PL1 is connected to scan driver 110); and an emission driving circuit connected to the emission control line (emission driver 130), wherein the pixel (referring to fig.7) includes: a light emitting element (LED) including an anode (anode) connected to the first power line (VDD) and a cathode (cathode); a first transistor connected between the cathode and the second power line (T17 connected between VSS and cathode of LED 30), wherein the first transistor operates based on a potential of a first node (N13); a second transistor connected between a second node and the data line (T11 between node N12 and data line D[j]), and connected to the first scan line (S[i]); a first capacitor between the first node and the second node (Cst); a third transistor connected between a first electrode of the first transistor and the first node (T16 between N13 and T17), and connected to the second scan line (p[i]); an emission control transistor connected between the first electrode of the first transistor and the cathode, and connected to the emission control line (T15 connected to P[i]); and a fourth transistor connected to the second node and the second scan line and configured to initialize the second node in response to a second scan signal transmitted thereto through the second scan line during an initialization period (T12 in response to the scan signa S[i] N11 as the initialized node, para 0149).
CHO does not disclose “a second capacitor connected between the second node and the first power line.”
KIM discloses a second capacitor connected between the second node and the first power line (fig. 1, C1 connected to between ELVDD and node N1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing of the application, to use KIM’s teachings of in CHO’s invention to reduce leakage currents of the transistors and display with uniform luminance, para 0100, KIM.
In regard to claims 2, 16, CHO as modified by KIM discloses the display device of claim 1, the display device of claim 15, wherein the pixel further includes: a fifth transistor which initializes the cathode in response to a third scan signal during a cathode initialization period (T14 connected to EM[i]); and an emission control transistor connected between the first electrode of the first transistor and the cathode, wherein the emission control transistor receives an emission control signal (T15 connected to P[i]).
In regard to claim 18, CHO as modified by KIM discloses the display device of claim 15, wherein the pixel further includes: a fifth transistor (T14) connected to the first electrode of the first transistor (connected to T17) and a third scan line (p[j]), wherein the fifth transistor initializes the first electrode of the first transistor in response to a third scan signal during a cathode initialization period (T14 helps to pre-charge a first transistor T17 at node N13 using P[j]), and wherein the emission control transistor receives an emission control signal (T15 receives P[i]).
In regard to claim 17, CHO as modified by KIM discloses the display device of claim 16, wherein the second scan driving circuit provides the third scan signal to the third scan line (Scan driver 110 as an equivalent second scan driving circuit sends the second scan signal p[i] i.e. it integrally discloses both first and second scan drivers. No specific structure of the second scan driver is claimed.).
In regard to claim 19, CHO as modified by KIM discloses the display device of claim 18, further comprising: a third scan driving circuit which provides the third scan signal to the third scan line (Scan driver 110 as an equivalent third scan driving circuit sends the third scan signal p[j] i.e. it integrally discloses both first and second and third scan drivers. No specific structure of the second and/or third scan driver is claimed.).
In regard to claim 6, CHO as modified by KIM discloses the display device of claim 2, wherein the fifth transistor includes: a first electrode connected to the first power line (T14 connected to VDD, CHO); a second electrode connected to the cathode (T14 connected to cathode of LED in the circuit configuration, CHO); and a gate electrode configured to receive the third scan signal (gate electrode of T14 connected to P[j],CHO).
In regard to claim 7, CHO as modified by KIM discloses the display device of claim 2, wherein the fifth transistor includes: a first electrode connected to a first initialization voltage line which transmits a first initialization voltage (T14, CHO); a second electrode connected to the cathode (T14 connected to cathode of LED, CHO); and a gate electrode configured to receive the third scan signal (connected to p[j]).
In regard to claim 8, CHO as modified by KIM discloses the display device of claim 1, wherein the fourth transistor (T12 in response to the scan signa S[i] N11 as the initialized node, para 0149, CHO) includes: a first electrode connected to the second node (N11,CHO); a second electrode connected to the second power line (VDD,CHO); and a gate electrode configured to receive the second scan signal (connected to S[i],CHO).
In regard to claim 9, CHO as modified by KIM discloses the display device of claim 1, wherein the fourth transistor includes: a first electrode connected to the second node; a second electrode connected to a second initialization voltage line which transmits a second initialization voltage and a gate electrode which receives the second scan signal (T12 in response to the scan signa S[i] N11 as the initialized node, para 0149 and para 0146 is connected to an initialization voltage Vint, CHO).
In regard to claim 11, CHO as modified by KIM discloses the display device of claim 1, wherein the pixel further includes: a fifth transistor (fifth transistor T14, CHO) which initializes the first electrode of the first transistor (T17,CHO) in response to a third scan signal (p]j],CHO) during a first initialization period; and an emission control transistor connected between the first electrode of the first transistor and the cathode, wherein the emission control transistor receives an emission control signal (T15 connected to P[i],CHO and also connected to T17).
In regard to claim 12, CHO as modified by KIM discloses the display device of claim 11, wherein the fifth transistor (fifth transistor T14, CHO) includes: a first electrode connected to the first power line (connected VDD, CHO); a second electrode connected to the first electrode of the first transistor (connect to T17); and a gate electrode which receives the third scan signal (see interpretation above for indirect electrical connection: gate electrode connected to P[j],CHO).
Allowable Subject Matter
Claims 3-5, 10 and 13-14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
In regard to claim 3, CHO as modified by KIM discloses the display device of claim 2, CHO as modified by KIM does not disclose “wherein the third scan signal is activated before the second scan signal, wherein during the cathode initialization period, the third scan signal and the emission control signal have active levels, and the first scan signal and the second scan signal have inactive levels, wherein during the initialization period lagging behind the cathode initialization period, the second scan signal, the third scan signal, and the emission control signal have active levels, and the first scan signal has an inactive level, and wherein the cathode is initialized during the cathode initialization period, and the cathode, the first node, and the second node are initialized during the initialization period” as a whole.
Claims 4-5 depend on claim 3.
In regard to claim 10, CHO as modified by KIM discloses the display device of claim 1, CHO as modified by KIM does not disclose “wherein the pixel further includes: a fifth transistor which initializes the cathode in response to the second scan signal during the initialization period; and an emission control transistor connected between the first electrode of the first transistor and the cathode, wherein the emission control transistor receives an emission control signal, wherein during the initialization period, the second scan signal and the emission control signal have active levels, and the first scan signal has an inactive level, and wherein the cathode, the first node, and the second node are initialized during the initialization period” as a whole.
In regard to claim 13, CHO as modified by KIM discloses the display device of claim 11, CHO as modified by KIM does not disclose “wherein the third scan signal is activated before the second scan signal, wherein during the first initialization period, the third scan signal and the emission control signal have active levels, and the first scan signal and the second scan signal have inactive levels, wherein during a second initialization period after the first initialization period, the second scan signal, the third scan signal, and the emission control signal have active levels, and the first scan signal has an inactive level, and wherein the first electrode of the first transistor is initialized during the first initialization period, and the first electrode of the first transistor and the first node and the second node are initialized during the second initialization period” as a whole.
Claim 14 depend on claim 13.
Conclusion
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/DEEPROSE SUBEDI/Primary Examiner, Art Unit 2627