DETAILED ACTION
This action is responsive to the application filed on 6/25/2025. Claims 1-14 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1-14 are objected to because of the following informalities:
In regard to claim 1, lines 9- 10 amend “the at least one condition” to “the at least one branch condition” as to use language consistent with line 6 and correct a minor antecedent basis issue.
In regard to claim 1, lines 4, 8 and 11 remove the capitalized letters in “Executing”, “Predicting” and “Inserting” as to improve grammar.
In regard to claim 8, line 3 amend “the at least one condition” to “the at least one branch condition” as to use language consistent with claim 1, line 6 and correct a minor antecedent basis issue.
In regard to claim 10, line 3 amend “the at least one condition” to “the at least one branch condition” as to use language consistent with claim 1, line 6 and correct a minor antecedent basis issue.
In regard to claim 11, line 3 amend “the at least one condition” to “the at least one branch condition” as to use language consistent with claim 1, line 6 and correct a minor antecedent basis issue.
In regard to claim 12, last line amend the limitation to state “a method according to claim 1” as to improve readability and correct a minor clarity issue.
Claims 2-14 are dependent upon one or more claims above and thus are objected to for including the deficiencies of one or more claims above.
Appropriate correction is required.
Claim Interpretation
4. Claim 1 recites the following contingent limitations: “…Predicting, by the processing unit, at least one of the pre-branch instructions (A) and/or a target instruction (T) to be executed as the subsequent instruction if the at least one condition is met; and Inserting, by the processing unit, the at least one predicted pre-branch instruction (A) and/or the target instruction (T) into the instruction set (I) after the conditional branch (C).”
The contingent limitations use the language “if” and are contingent because they precede steps that are only required to be performed responsive to (i.e. if) a condition is met. For example, the steps of “Predicting, by the processing unit, at least one of the pre-branch instructions (A) and/or a target instruction (T) to be executed as the subsequent instruction” and “Inserting, by the processing unit, the at least one predicted pre-branch instruction (A) and/or the target instruction (T) into the instruction set (I) after the conditional branch (C)” are only required to be performed if the branch condition is met. However, if the branch condition is not met the steps of “predicting the pre-branch instructions to be executed as the subsequent instruction” and “inserting the predicted pre-branch instruction after the conditional branch” are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)).
The examiner suggests amending the claim to remove the contingent limitations and to positively recite each step of the method claim. (for example, applicant could amend the claim to include a limitation stating “determining that the at least one branch condition is met; predicting, by the processing unit, at least one of the pre-branch instructions (A) and/or a target instruction (T) to be executed as the subsequent instruction in response to the determining
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-3, 6, 8-10 and 12-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Blasco, PGPUB No. 2024/0385841.
In regard to claim 1, Blasco discloses A method for deterministic execution of an instruction set (I) containing instructions (M) to be carried out by a processing unit (11) of a computing device (2) ([0019-0028]: wherein execution of instructions, to be carried out by processing circuit (element 104) of device (element 100), is determined (See Figs. 1-2)) the method comprising the steps of Executing, by the processing unit, a predefined number of pre-branch instructions (A) up to a conditional branch (C) of the instruction set (I) containing at least one branch condition ([0028-0031]: wherein an instruction stream, containing instructions (element 202) up to a conditional branch (element 202(x)) containing at least one branch condition, are executed) determining a subsequent instruction which is to be executed after the conditional branch (C) ([0028-0031]: wherein a subsequent instruction which is to be executed after the conditional branch is determined based on whether the branch is predicted taken or not taken based on the at least one branch condition being met or not (See Fig. 2)) Predicting, by the processing unit, at least one of the pre-branch instructions (A) and/or a target instruction (T) to be executed as the subsequent instruction if the at least one condition is met ([0028-0031]: wherein if the conditional branch is predicted taken based on condition being met at least one of the pre-branch instructions (element 202) in a loop are executed as the subsequent instruction (also see [0024-0027] for further details of conditional branch prediction)) and Inserting, by the processing unit, the at least one predicted pre-branch instruction (A) and/or the target instruction (T) into the instruction set (I) after the conditional branch (C). ([0028-0032]: wherein a copy of the pre-branch instructions in a predicted taken path (element 202’) are inserted after the conditional branch in the instruction stream via a fetch bundle (See Fig. 1-2))
In regard to claim 2, Blasco discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one predicted pre-branch instruction (A) and/or target instruction (T) is added to the instruction set (I) and executed subsequent to the conditional branch (C). ([0028-0032]: wherein at least one pre-branch instruction, in the predicted taken path in the loop, is added to the instruction stream via fetch bundle and executed subsequent the conditional branch)
In regard to claim 3, Blasco discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one predicted pre-branch instruction (A) and/or target instruction (T) is being copied for insertion. ([0028-0032]: wherein at least one predicted pre-branch instruction is copied for insertion (See Fig. 2))
In regard to claim 6, Blasco discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one inserted pre-branch instruction (A), and/or target instruction (T) is being executed using a memory pointer used by the respective at least one pre-branch instruction (A) and/or target instruction (T). ([0028, 0030-0031 and 0034]: wherein the inserted pre-branch instructions (202’) are being executed using a PC value (memory pointer) used by the pre-branch instructions (202))
In regard to claim 8, Blasco discloses The method according to claim 1 (see rejection of claim 1 above) wherein a predefined number of the pre-branch instructions (A) up to the conditional branch (C) is configured to be executed in a loop (L) as long as the at least one condition is met. ([0028-0032]: wherein a predefined number of pre-branch instructions (elements 202) up to conditional branch (element 202(x)) is configured to be executed in a loop as long as a condition is satisfied (See Fig. 2))
In regard to claim 9, Blasco discloses The method according to claim 8 (see rejection of claim 8 above) wherein from the conditional branch (C), the loop (L) returns to a pre-branch instruction (A) to be executed before the conditional branch (C) and following the at least one pre-branch instruction (A) and/or target instruction (T) that is inserted after the conditional branch (C). ([0028-0033]: wherein from the predicted taken branch the loop returns to instruction (202(0))executed before the conditional branch (202(x)) and following the inserted pre-branch instructions (202’) inserted after the conditional branch (202(x)) when only a single copy fits in the fetch bundle and an additional iteration of the loop is required (See Figs. 1-3))
In regard to claim 10, Blasco discloses The method according to claim 1 (see rejection of claim 1 above) wherein a post-branch instruction (B) following the at least one inserted pre-branch instruction (A) and/or target instruction (T) is being executed if the at least one condition is not met. ([0024, 0028 and 0030]: wherein an instruction in a not-taken path of a branch (post-branch instruction) following the inserted pre-branch instructions (202’(0)) is executed if a condition is not met)
In regard to claim 12, Blasco discloses A non-transitory computer-readable data-carrier having stored thereon a computer program comprising instructions which, when the program is executed by a computing device ([0011, 0042 and 0044]) cause the computing device to carry out a method according to 1. (see rejection of claim 1 above)
In regard to claim 13, Blasco discloses A computing device comprising a computer-readable data-carrier ([0011, 0042 and 0044]) according to claim 12. (see rejection of claim 12 above)
In regard to claim 14, Blasco discloses An apparatus comprising a vehicle or an aircraft ([0038]) comprising a computing device according to claim 13. (see rejection of claim 13 above)
7. Claim(s) 1 and 3-11 is/are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Anderson, EP0840208 B1 (cited on IDS filed on 6/30/2025).
In regard to claim 1, Anderson discloses A method for deterministic execution of an instruction set (I) containing instructions (M) to be carried out by a processing unit (11) of a computing device (2) ([0018-0020]: wherein execution of an instruction stream to be carried out by a microprocessor of a system is disclosed (See Figs. 2 and 4)) the method comprising the steps of Executing, by the processing unit, a predefined number of pre-branch instructions (A) up to a conditional branch (C) of the instruction set (I) containing at least one branch condition ([0018-0020]: wherein a number of pre-branch instructions (TR-C) up to a short branch containing at least one branch condition (see Fig. 2) are executed) determining a subsequent instruction which is to be executed after the conditional branch (C) ([0018-0020]: wherein a BTB is used to determine a subsequent instruction to be executed after the short backward branch (See Fig. 2)) Predicting, by the processing unit, at least one of the pre-branch instructions (A) and/or a target instruction (T) to be executed as the subsequent instruction if the at least one condition is met ([0018-0020]: wherein microprocessor system uses a BTB to predict if a short backward branch forms a loop that is taken and would thus cause pre-branch instructions to be subsequently executed if a condition is met (See Fig. 4)) and Inserting, by the processing unit, the at least one predicted pre-branch instruction (A) and/or the target instruction (T) into the instruction set (I) after the conditional branch (C). ([0037-0041]: wherein at least one instruction of a second iteration of the loop (e.g. TR2-B2, predicted taken pre-branch instructions) is inserted into the instruction stream/pipeline after the conditional branch using queue (30)))
In regard to claim 3, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one predicted pre-branch instruction (A) and/or target instruction (T) is being copied for insertion. ([0037-0041]: wherein the instructions of a second iteration of the loop (e.g. TR2-B2, predicted taken pre-branch instructions) are copied for insertion as these instructions are duplicates of the first iteration of instructions, thus are copied for insertion into the stream/pipeline)
In regard to claim 4, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one inserted pre-branch instruction (A) and/or target instruction (T) is being executed while assessing whether the branch condition is met. ([0030 and 0037-0041]: wherein the instructions of a second iteration of the loop (e.g. TR2-B2, predicted taken pre-branch instructions) are executed in the same cycle as the short backward branch and thus the branch is being executed to assess whether the branch condition has been met or not (e.g. determining actual branch target or misprediction) (See Fig. 4))
In regard to claim 5, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one inserted pre-branch instruction (A) and/or target instruction (T), and a branch instruction for assessing the at least one branch condition are being executed in parallel. ([0030 and 0037-0041]: wherein the instructions of a second iteration of the loop (e.g. TR2-B2, predicted taken pre-branch instructions) are executed simultaneously with a short backward branch for assessing at least one branch condition)
In regard to claim 6, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein the at least one inserted pre-branch instruction (A), and/or target instruction (T) is being executed using a memory pointer used by the respective at least one pre-branch instruction (A) and/or target instruction (T). ([0047-0050]: wherein inserted instructions of second iteration of loop ( such as TR2) are being executed using a memory cell pointer (cell address 2) used by respective pre-branch instruction (TR) (see Fig. 6b-6c))
In regard to claim 7, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein a memory address of the at least one inserted pre-branch instruction (A) and/or target instruction (T) is being set to the respective memory address of the pre-branch instruction (A) and/or target instruction (T), respectively. ([0047-0050]: wherein a memory address (cell address 2) of an instruction of second iteration of loop ( such as TR2) is set to a memory address (cell address 2) used by respective pre-branch instruction (TR) (see Fig. 6b-6c))
In regard to claim 8, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein a predefined number of the pre-branch instructions (A) up to the conditional branch (C) is configured to be executed in a loop (L) as long as the at least one condition is met. ([0018-0020] (See Fig. 2))
In regard to claim 9, Anderson discloses The method according to claim 8 (see rejection of claim 8 above) wherein from the conditional branch (C), the loop (L) returns to a pre-branch instruction (A) to be executed before the conditional branch (C) and following the at least one pre-branch instruction (A) and/or target instruction (T) that is inserted after the conditional branch (C). ([0037-0041]: wherein from short backward branch the loop returns to a pre-branch instruction (TR3) to be executed before short backward branch and following the inserted pre-branch instruction (TR2-B2))
In regard to claim 10, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) wherein a post-branch instruction (B) following the at least one inserted pre-branch instruction (A) and/or target instruction (T) is being executed if the at least one condition is not met. ([00018-0020, 0028 and 0044]: wherein a post-branch instruction (M) following instructions of second iteration of a loop is executed if branch is not taken (See Fig. 2))
In regard to claim 11, Anderson discloses The method according to claim 1 (see rejection of claim 1 above) further comprising the step of discarding a processing result of an execution of the inserted pre-branch instructions (A) and/or target instruction (T) if the at least one condition is not met. ([0028 and 0044]: wherein a pipeline flush occurs to discard execution results of inserted pre-branch instructions if it is determined that a branch mispredicted because a branch taken condition is not met (e.g. branch is not taken))
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
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