Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 8-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022.01014852) in view of Cho (US 2021.0036082)
Regarding claim 1, Kim disclose:
A display panel comprising: a first driving circuit comprising first stages arranged along a first direction; a second driving circuit comprising second stages arranged along the first direction; (see Fig. 1, 4, 8; [0193-0196]; display panel 10; first driving circuit EMI_D 2001; second driving circuit EM2_D 2002; each arranged a long a first (vertical column) direction)
at least one clock line between the first driving circuit and the second driving circuit, and extending along the first direction, wherein the first stages and the second stages comprise: semiconductor transistors and conductive patterns (see Fig. 1, 4, 8; [0193-0196]; at least one clock line CLK1, CLK2 arranged between 2001 and 2002 in the first vertical direction, where each stage comprises semiconductive transistors and conductive patterns adjacent thereto)
Kim is not explicit as to, but Cho disclose:
While Kim includes a semiconductive transistors and conductive patterns adjacent thereto, it does not explicitly recite an oxide semiconductor transistor comprising an oxide semiconductor layer, and a gate electrode overlapping portions of the oxide semiconductor layer; and a conductive pattern adjacent to the oxide semiconductor transistor, and at a same layer as the gate electrode. However, Cho at Fig. 10b, 10e and [0123-0124] discloses: oxide semiconductor TFT T1 with oxide semiconductive layer OSP; gate electrode GE1 overlapping OSP; conductive pattern LSP adjacent to T1 and on same layer 10 as GE1. Since each individual element is shown in the prior art, albeit in separate references, the difference between the claimed subject matter and the prior art rests not in any individual element of unction but in the very combination, in the substitution of the oxide semiconductor of Cho to that of the semiconductor transistor of Kim. Thus the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Regarding claim 2, the rejection of claim 1 is incorporated herein. Cho further disclose:
the oxide semiconductor layer comprises a first area, an active area, and a second area spaced apart from the first area with the active area therebetween, and wherein the display panel further comprises a first signal electrode electrically connected to the first area, and a second signal electrode electrically connected to the second area (see Fig. 10b, 10e; first area DE1 active area OPS1, second area SE1; first/second signal electrode SGL connected via CH1 and CH2).
Regarding claim 3, the rejection of claim 2 is incorporated herein. Cho further disclose:
the conductive pattern comprises an electrically floated island shape (see Fig. 10B; [0124]; LSP “island shape” is floated).
Regarding claim 4, the rejection of claim 3 is incorporated herein. Cho further disclose:
the conductive pattern partially surrounds at least a portion of the first area in plan view (see Fig. 10B; where LSP being adjacent to T1, thus ‘partially’ surrounds at least a portion of DE1)
Regarding claim 5, the rejection of claim 2 is incorporated herein. Cho further disclose:
the conductive pattern is electrically connected to the second signal electrode (see Fig. 10E; LSP electrically connected to second signal electrode SGL via CH7).
Regarding claim 8, the rejection of claim 1 is incorporated herein. Kim further disclose:
at least one clock line comprises a first clock line, and a second clock line spaced apart from the first clock line in a second direction crossing the first direction (see Fig. 8; CLK1 spaced from CLK2 in second direction).
Regarding claim 9, the rejection of claim 8 is incorporated herein. Cho further disclose:
a dummy semiconductor pattern at a different layer from the oxide semiconductor layer; and an intermediate insulation layer covering the dummy semiconductor pattern, and defining a dummy through-hole adjacent to the oxide semiconductor layer and exposing at least a portion of the dummy semiconductor pattern (see Fig. 10E; dummy semiconductor pattern LSP; different layer than OSP1 with insulation layer 20 covering OSP and defining a through hole CH7 adjacent to SOP and exposing LSP).
Regarding claim 10, the rejection of claim 9 is incorporated herein. Cho further disclose:
the dummy semiconductor pattern comprises a low-temperature poly silicon semiconductor (see [0071, 0121, 0139]; polysilicon in T1; LSP and OSP same material - it would have been obvious to try by one of ordinary skill in the art at the time of applicant’s filing, since there are a finite number of identified, predictable potential solutions (e.g., LSP and OPS to be same material) to be pursued by one of ordinary skill in the art with a reasonable expectation of success.)
Regarding claim 11, the rejection of claim 9 is incorporated herein. Cho further disclose:
the oxide semiconductor layer is above the intermediate insulation layer (see Fig. 10E; where OSP is above 20 in direction DR3)
Regarding claim 12 the rejection of claim 9 is incorporated herein. Cho further disclose:
dummy semiconductor LSP, except for LSP pattern provided in plural. It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide a plurality of dummy patterns spaced part along a first direction, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 14, the rejection of claim 9 is incorporated herein. While Cho at [0052] describe oxide semiconductive pattern OSP and conductive pattern LSP having the same material and at [0121] where OSP comprises titanium, it is not explicit that LSP be titanium, thus it would have been obvious to try by one of ordinary skill in the art at the time of applicant’s filing, since there are a finite number of identified, predictable potential solutions (e.g., titanium conductive pattern) to be pursued by one of ordinary skill in the art with a reasonable expectation of success.
Allowable Subject Matter
Claims 15-20 allowed. As to claim 15, the recitation of “…a first driving circuit electrically connected to the pixels, and comprising a first stage; a second driving circuit electrically connected to the pixels, and comprising a second stage; and a dummy semiconductor pattern between the first stage and the second stage in plan view, wherein the first stage and the second stage comprise an oxide semiconductor transistor comprising an oxide semiconductor layer and a gate electrode, and a conductive pattern, and wherein the conductive pattern and the dummy semiconductor pattern are adjacent to the oxide semiconductor layer in plan view” cannot be found alone or in combination within the cited prior art.
Claims 6-7 and 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH BUKOWSKI whose telephone number is (571)270-7913. The examiner can normally be reached Monday - Friday // 0730-1530.
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/kenneth bukowski/Primary Examiner, Art Unit 2621
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