DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (US Pub. No. 2019/0113393).
a) regarding claim 1:
Sato et al. discloses a temperature sensing circuit (Figure 7), comprising:
a temperature sensor (702); and
a control circuit (703) coupled to the temperature sensor and comprising:
a sampling circuit coupled to the temperature sensor and configured to obtain a first voltage information and a second voltage information from the temperature sensor (paragraph [0046], “In this manner the first and second sample and hold capacitors are charged to the voltages at node 710 when currents I1 and I2 flow through stand 702, respectively.”); and
a computing circuit coupled to the sampling circuit and configured to generate a sensing result corresponding to a difference between the second voltage information and the first voltage information (paragraph [0046], “The first and second sample and hold capacitors can be connected to respective inputs of the differential amplifier, so that the differential amplifier generates analog Vout as a difference between the voltages held by the first and second sample and hold capacitors, respectively. An ADC can be provided that generates a digital equivalent of Vout for subsequent processing by a CPU to yield a digital value for T based on equation (3) above.”).
b) regarding claim 2:
Sato et al. discloses the temperature sensing circuit of claim 1, wherein the temperature sensor comprises a diode connected bipolar junction transistor (BJT) (206).
c) regarding claim 3:
Sato et al. discloses the temperature sensing circuit of claim 2, wherein the first voltage information and the second voltage information comprise voltage differences across the diode connected BJT when a first current and a second current are respectively provided to the temperature sensor in different time periods (paragraph [0046]).
d) regarding claim 4:
Sato et al. discloses the temperature sensing circuit of claim 1, wherein a voltage level of the sensing result corresponds to a temperature sensed by the temperature sensor (paragraph [0046]).
e) regarding claim 5:
Sato et al. discloses the temperature sensing circuit of claim 1, wherein the computing circuit comprises a voltage subtractor (differential amplifier) configured to generate the sensing result by subtracting the second voltage information from the first voltage information (paragraph [0046]).
f) regarding claim 8:
Sato et al. discloses (Figure 7) a control circuit (703) for controlling a temperature sensor (702), the control circuit comprising:
a sampling circuit coupled to the temperature sensor and configured to obtain a first voltage information and a second voltage information from the temperature sensor (paragraph [0046], “In this manner the first and second sample and hold capacitors are charged to the voltages at node 710 when currents I1 and I2 flow through stand 702, respectively.”); and
a computing circuit coupled to the sampling circuit and configured to generate a sensing result corresponding to a difference between the second voltage information and the first voltage information (paragraph [0046], “The first and second sample and hold capacitors can be connected to respective inputs of the differential amplifier, so that the differential amplifier generates analog Vout as a difference between the voltages held by the first and second sample and hold capacitors, respectively. An ADC can be provided that generates a digital equivalent of Vout for subsequent processing by a CPU to yield a digital value for T based on equation (3) above.”).
g) regarding claim 15:
Sato et al. discloses a method for obtaining temperature information about a circuit (Figure 7), the method comprising:
providing a first current (302) and a second current (304) in different time periods to a temperature sensor (702) associated with the circuit;
obtaining a first voltage information and a second voltage information from the temperature sensor when the first current and second current are respectively provided (paragraph [0046], “In this manner the first and second sample and hold capacitors are charged to the voltages at node 710 when currents I1 and I2 flow through stand 702, respectively.”); and
generating the temperature information based on the first and second voltage information (paragraph [0046], “The first and second sample and hold capacitors can be connected to respective inputs of the differential amplifier, so that the differential amplifier generates analog Vout as a difference between the voltages held by the first and second sample and hold capacitors, respectively. An ADC can be provided that generates a digital equivalent of Vout for subsequent processing by a CPU to yield a digital value for T based on equation (3) above.”).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,416,529 (hereinafter ‘529 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because other because the present claims are a broader recitation of the '529 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use the teachings of claims 1-20 of the '529 patent as general teachings of a temperature sensor circuit as claimed in the present application. The instant claims obviously encompass the claimed invention in the '529 patent and differ only in terminology.
Conclusion
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/PATRICK O NEILL/Primary Examiner, Art Unit 2836
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