DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the Continuation filed on 06/27/2025
This is a CON of 18/213,320 which is now a PAT 12,480,456 B2 which is a DIV of 17/382,571 which is now a PAT 11,728,362 B2
Application claims a DP date of 04/22/2021
Claims 1-20 are pending
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/27/2025 and 02/03/2026 are in compliance with the provisions of 37 CFR 1.97 and 37 CFR 1.98(a)(4). Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent Number 11,728,362 B2 and over claims 1-20 of U.S. Patent Number 12,408,456 B2. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the following table.
1. Application: A method for providing an image sensor pixel, the method comprising: providing a photosensitive device and a charge storage device and at least one dielectric layer covering the photosensitive device and the charge storage device;
1. Patent 11,728,362 B2: A method for providing an image sensor pixel, the method comprising: providing a photosensitive device and a charge storage device and a dielectric layer covering the photosensitive device and the charge storage device,
etching the at least one dielectric layer to define an undercut volume in the at least one dielectric layer and an access opening through the at least one dielectric layer to the undercut volume; and
1. Patent 11,728,362 B2: performing etching of the dielectric layer to define an undercut volume beneath the dielectric layer while leaving an overhanging region of the dielectric layer that overhangs the undercut volume, and
depositing a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and
1. Patent 11,728,362 B2: after the etching, performing physical vapor deposition (PVD) of a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and
fill the access opening with the light blocking material to form a light blocking plug.
1. Patent 11,728,362 B2: fill the access opening with the light blocking material to form a light blocking plug
2. Application: wherein the depositing is by physical vapor deposition
1. Patent 11,728,362 B2: performing physical vapor deposition (PVD) of a light blocking material
3. Application: wherein the depositing forms the light blocking layer and the light blocking plug as a contiguous structure made of the light blocking material
3. Patent 11,728,362 B2: wherein the PVD forms the light blocking layer and the light blocking plug as a contiguous structure made of the light blocking material
4. Application: wherein the depositing consists of a single deposition operation
4. Patent 11,728,362 B2: wherein the PVD consists of a single deposition operation
5. Application: wherein: the at least one dielectric layer includes a first dielectric layer of a first material disposed over the photosensitive device and the charge storage device and a second dielectric layer of a second material different from the first dielectric material disposed over the first dielectric layer, and
1. Patent 11,728,362 B2: wherein the dielectric layer includes a first dielectric layer of a first material disposed over the photosensitive device and the charge storage device and a second dielectric layer of a second material different from the first dielectric material disposed over the first dielectric layer;
the etching includes performing a selective etch that selectively etches the first material over the second material to define the undercut volume.
1. Patent 11,728,362 B2: wherein the etching includes performing a first etch that etches through the first dielectric layer and the second dielectric layer, the first etch defining the access opening through the dielectric layer, and a second etch that selectively etches the first material over the second material to define the undercut volume;
6. Application: wherein the first material comprises a borophosphosilicate glass (BPSG) and the second material comprises a plasma enhanced tetraethoxysilane (PE-TEOS), and the undercut volume is in the first dielectric layer comprising BPSG.
14. Patent 11,728,362 B2: wherein the first material comprises a borophosphosilicate glass (BPSG) and the second material comprises a plasma enhanced tetraethoxysilane (PE-TEOS)
7. Application: wherein the light blocking plug passes through the at least one dielectric layer and contacts the light blocking layer.
5. Patent 11,728,362 B2: wherein the light blocking plug passes through the at least one dielectric layer and contacts the light blocking layer.
8. Application: wherein the light blocking layer and the light blocking plug comprise a contiguous structure that is made of a metal or of a multilayer.
9. Patent 11,728,362 B2: wherein the light blocking layer and the light blocking plug comprise a contiguous structure that is made of a metal or of a multilayer.
9. Application: further comprising: providing a shutter gate transistor connected to reset the photosensitive device;
8. Patent 11,728,362 B2: further comprising: providing a shutter gate transistor connected to reset the photosensitive device;
providing a charge transfer path including a transfer gate transistor via which electrical charge from the photosensitive device transfers to charge storage device; and
8. Patent 11,728,362 B2: providing a charge transfer path including a transfer gate transistor via which electrical charge from the photosensitive device transfers to charge storage device; and
providing readout circuitry configured to read out electrical charge stored in the charge storage device.
8. Patent 11,728,362 B2: providing readout circuitry configured to read out electrical charge stored in the charge storage device.
10. Application: wherein the light blocking material comprises a multilayer.
10. Patent 11,728,362 B2: wherein the light blocking material comprises a multilayer.
11. Application: wherein the light blocking material comprises a titanium/titanium nitride/tungsten (Ti/TiN/W) multilayer, and
11. Patent 11,728,362 B2: wherein the bump part is composed of a metal wire
the deposition of the light blocking material is by physical vapor deposition and includes varying the flows of triethylborate (TEB), tetraethoxysilane (TEOS), and triethylphosphate (TEPO).
12. Patent 11,728,362 B2: wherein the PVD of the light blocking material comprising the titanium/titanium nitride/tungsten multilayer includes varying the flows of TEB, TEOS and TEPO
12. Application: wherein the providing of the photosensitive device and the charge storage device and the dielectric layer covering the photosensitive device and the charge storage device includes:
15. Patent 11,728,362 B2: the providing of the photosensitive device and the charge storage device and the dielectric layer covering the photosensitive device and the charge storage device including
depositing a contact etch stop layer over the photosensitive device and the charge storage device; and depositing the at least one dielectric layer over the contact etch stop layer.
15. Patent 11,728,362 B2: depositing a contact etch stop layer over the photosensitive device and the charge storage device and depositing the dielectric layer over the contact etch stop layer
13. Application: wherein the contact etch stop layer comprises silicon nitride, carbon-doped silicon nitride, or a combination thereof.
16. Patent 11,728,362 B2: wherein the contact etch stop layer comprises silicon nitride, carbon-doped silicon nitride, or a combination thereof.
14. Application: wherein the depositing of the contact etch stop layer comprises depositing the contact etch stop layer by chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, or molecular layer deposition.
17. Patent 11,728,362 B2: wherein the depositing of the contact etch stop layer comprises depositing the contact etch stop layer by chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, or molecular layer deposition.
Claims 15-20 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent Number 11,728,362 B2 and over claims 1-20 of U.S. Patent Number 12,408,456 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-11 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (U.S. Patent Publication Number 2019/0393255 A1) in view of Lenchenkov et al. (U. S. Patent Publication Number 2017/0005121 A1).
Regarding Claim 1, LEE discloses a method for providing an image sensor pixel (Lee’s disclosure is about “method for forming a global shutter CMOS image sensor”), the method comprising:
providing a photosensitive device (Fig 1A – CMOS image sensor 100 having a photodiode 104) and a charge storage device (Fig 1A – storage diode 106) and at least one dielectric layer covering the photosensitive device and the charge storage device (Fig 1A – first dielectric layer 114; In ¶0026, Lee discloses about forming the first dielectric layer 114 on the substrate 102);
etching the at least one dielectric layer (In ¶0026, Lee further discloses etching back process on the first dielectric layer 114) to define an undercut volume in the at least one dielectric layer and an access opening through the at least one dielectric layer to the undercut volume (This is disclosed by Lee in Fig 3 and in ¶0030 where he discloses the etching process of the dielectric layer 114 to form a hole 118); and
depositing a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device (He further discloses that in some embodiments the light pipe material may be deposited on the light-shielding layer 116 and filled in the hole 118 using physical vapor deposition PVD),
However, LEE fails to clearly disclose fill the access opening with the light blocking material to form a light blocking plug.
Instead in a similar endeavor, Lenchenkov discloses fill the access opening with the light blocking material to form a light blocking plug (In Fig 4 and in ¶0031, ¶0033 Lenchenkov teaches about light shield 352 and also the trench isolation 350 structures formed by digging a trench or cavity and filling the cavity with optically absorptive material).
LEE and Lenchenkov are combinable because both are about photoelectric conversion apparatus and methods.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dig trench isolation structures overlapping the storage diode regions SD as taught by Lenchenkov in the imaging module disclosed by LEE.
The suggestion/motivation for doing so would have been to “shield the storage regions so that incoming light can be effectively absorbed without being reflected or scattered” as disclosed by Lenchenkov throughout his disclosure and especially in ¶0031, ¶0034.
Therefore, it would have been obvious to combine LEE and Lenchenkov to obtain the invention as specified in claim 1.
Regarding Claim 2, LEE in view of Lenchenkov discloses wherein the depositing is by physical vapor deposition (Lee: In ¶0031 Lee discloses that a material with high refractive index such as greater than 1.45 is filled in the hole 118; He further discloses that in some embodiments the light pipe material may be deposited on the light-shielding layer 116 and filled in the hole 118 using physical vapor deposition PVD)
Regarding Claim 3, LEE in view of Lenchenkov discloses wherein the depositing forms the light blocking layer and the light blocking plug as a contiguous structure made of the light blocking material (Lee: He further discloses that in some embodiments the light pipe material may be deposited on the light-shielding layer 116 and filled in the hole 118 using physical vapor deposition PVD; Lenchenkov: Lenchenkov also in ¶0035 teaches that light shielding layer may be formed from optically absorptive material, similar to the material used to fill the trench, see ¶0034).
Regarding Claim 4, LEE in view of Lenchenkov discloses wherein the depositing consists of a single deposition operation (Lee: light-shielding layer 116 and filled in the hole 118 using physical vapor deposition PVD; Since Lee discloses PVD process, Lee discloses a single deposition operation).
Regarding Claim 5, LEE in view of Lenchenkov discloses wherein: the dielectric layer includes a first dielectric layer (Lee: Fig 1A – first dielectric layer 114;) of a first material disposed over the photosensitive device and the charge storage device (Lee: In ¶0026 Lee discloses that the first dielectric layer 114 includes oxides, spin-on lass (SOG), low-k dielectric material such as fluorinated silica glass (FSG) and hydrogen silesquioxane (HSQ)) and a second dielectric layer (Lee: Fig 10 – second dielectric layer 314;) of a second material different from the first dielectric material disposed over the first dielectric layer (Lee: Lee in ¶0049 discloses that in some embodiments, the material of the second dielectric layer 314 is different than that of the first dielectric layer 114), and the etching includes a-performing a selective etch that selectively etches the first material over the second material to define the undercut volume (Lee: Lee in Fig 10 clearly discloses that only the first dielectric layer 114 is selectively etched and not the second).
Regarding Claim 7, LEE in view of Lenchenkov discloses wherein the light blocking plug passes through the dielectric layer and contacts the light blocking layer (Lenchenkov: In Fig 4, Lenchenkov clearly teaches that the trench 350 passes through the substrate 310 and contacts the light shield 352; Lee: Lee also discloses that the hole 118 (Fig 3) or cavity 120 (Fig 10) is in contact with the light shield layer 116).
Regarding Claim 8, LEE in view of Lenchenkov discloses wherein the light blocking layer and the light blocking plug comprise a contiguous structure (Lenchenkov: In Fig 4, Lenchenkov clearly teaches that there is no gap between the trench 350 and the light shield 352; Lenchenkov, further, in ¶0035 teaches that light shielding layer may be formed from optically absorptive material, similar to the material used to fill the trench, see ¶0034).
Regarding Claim 9, LEE in view of Lenchenkov discloses further comprising:
providing a shutter gate transistor connected to reset the photosensitive device (Lenchenkov: Fig 2 – reset transistor RST 118; ¶0021);
providing a charge transfer path including a transfer gate transistor via which electrical charge from the photosensitive device transfers to charge storage device (Lenchenkov: Fig 2 – storage transistor SG 108, transfer transistor 114; ¶0022); and
providing readout circuitry configured to read out electrical charge stored in the charge storage device (Lenchenkov: Fig 2 – read out circuitry 102; ¶0023).
Regarding Claim 10, LEE in view of Lenchenkov discloses wherein the light blocking material comprises a multilayer (Lenchenkov: In ¶0034, Lenchenkov further teaches that they filler material could be metal silicide and some combination of these materials.).
Regarding Claim 11, LEE in view of Lenchenkov discloses wherein the light blocking material comprises a titanium/titanium nitride/tungsten (Ti/TiN/W) multilayer (Lenchenkov: In Fig 4, Lenchenkov clearly teaches that there is no gap between the trench 350 and the light shield 352; Lenchenkov, further, in ¶0035 teaches that light shielding layer may be formed from optically absorptive material, similar to the material used to fill the trench, see ¶0034; In ¶0034, Lenchenkov further teaches that they filler material could be metal silicide and some combination of these materials.), and the deposition of the light blocking material is by physical vapor deposition and includes varying the flows of triethylborate (TEB), tetraethoxysilane (TEOS), and triethylphosphate (TEPO) (Lenchenkov: In ¶0034, Lenchenkov further teaches that the optically absorptive material could be titanium oxide, tungsten and some combination of these materials.).
Regarding Claim 15, this claim is a “fabricating methods” claim which has limitations parallel to claims 1 and 5. Claim 15 is rejected on the same grounds as Claims 1 and 5.
Regarding Claim 16, LEE in view of Lenchenkov discloses wherein the forming of the photosensitive device comprises forming a P-N junction photodiode (Lee: Lee discloses this in ¶0020-¶0022).
Regarding Claim 17, LEE in view of Lenchenkov discloses wherein the filling of the access opening and the undercut volume comprises performing physical vapor deposition of the electrically conductive light blocking material (Lee: Lee further discloses that in some embodiments the light pipe material may be deposited on the light-shielding layer 116 and filled in the hole 118 using physical vapor deposition PVD; Further, in ¶0027, Lee discloses that the light shielding layer 116 is made of metal material which may include tungsten, aluminum etc. which are electrically conductive).
Regarding Claim 18, this claim is a “fabricating methods” claim which has limitations parallel to claims 1 and 5 (also Claim 15). Claim 18 is rejected on the same grounds as Claims 1 and 5.
Regarding Claim 19, this claim is a “fabricating methods” claim which has limitations parallel to claim 2. Claim 19 is rejected on the same grounds as Claim 2.
Regarding Claim 20, this claim is a “fabricating methods” claim which has limitations parallel to claim 6. Claim 20 is rejected on the same grounds as Claim 6.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over LEE (U.S. Patent Publication Number 2019/0393255 A1) in view of Lenchenkov et al. (U. S. Patent Publication Number 2017/0005121 A1) as applied to claim 1 above and further in view of Lee (U.S Patent Publication Number 2010/0285630 A1 – referred to as Lee-2010).
Regarding Claim 6, LEE in view of Lenchenkov fails to clearly disclose wherein the first material comprises a borophosphosilicate glass (BPSG) and the second material comprises a plasma enhanced tetraethoxysilane (PE-TEOS).
Instead in a similar endeavor, Lee-2010 discloses wherein the first material comprises a borophosphosilicate glass (BPSG) and the second material comprises a plasma enhanced tetraethoxysilane (PE-TEOS) (Lee-2010 in Fig 12 and in ¶0094 teaches that the first insulation layer 595 may include BPSG and in ¶0099 he teaches that the second insulation layer 610 may include PE-TEOS).
LEE, Lenchenkov and Lee-2010 are combinable because both are about photoelectric conversion apparatus and methods.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dig trench isolation structures overlapping the storage diode regions SD as taught by Lenchenkov and use BPSG and PE-TEOS as the first and second insulating layer as taught by Lee-2010 in the imaging module disclosed by LEE.
The suggestion/motivation for doing so would have been to “shield the storage regions so that incoming light can be effectively absorbed without being reflected or scattered” as disclosed by Lenchenkov throughout his disclosure and especially in ¶0031, ¶0034 and to use BPSG as a protection mask during the etching process as the presence of phosphorous is compatible with the deposition process with aluminum metallization.
Therefore, it would have been obvious to combine LEE, Lenchenkov and Lee-2010 to obtain the invention as specified in claim 6.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (U.S. Patent Publication Number 2019/0393255 A1) in view of Lenchenkov et al. (U. S. Patent Publication Number 2017/0005121 A1) as applied to claim 1 above and further in view of Tsao et al. (U.S Patent Publication Number 2018/0286905 A1).
Regarding Claim 12, LEE in view of Lenchenkov discloses wherein the providing of the photosensitive device (Lee: Fig 1A – photo diode 104; Lenchenkov: Fig 4 - PD) and the charge storage device (Lee: Fig 1A – storage diode 106; Lenchenkov: Fig 4 - SD) and the dielectric layer covering the photosensitive device and the charge storage device (Lee: Fig 3 – dielectric layer 114; Lenchenkov: Fig 4 – dielectric stack 312 and substrate 310).
LEE in view of Lenchenkov fails to clearly disclose depositing a contact etch stop layer over the photosensitive device and the charge storage device and depositing the dielectric layer over the contact etch stop layer.
Instead in a similar endeavor, Tsao discloses depositing a contact etch stop layer over the photosensitive device and the charge storage device (In ¶0025 and Fig 1B-1D Tsao teaches about the etch stop layer 160) and depositing the dielectric layer over the contact etch stop layer (Further in ¶0026 Tsao teaches about the conductive layer 162 and dielectric layer 166 made of anti-reflective material).
LEE, Lenchenkov and Tsao are combinable because both are about photoelectric conversion apparatus and methods.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dig trench isolation structures overlapping the storage diode regions SD as taught by Lenchenkov and use BPSG and PE-TEOS as the first and second insulating layer as taught by Tsao in the imaging module disclosed by LEE.
The suggestion/motivation for doing so would have been to “shield the storage regions so that incoming light can be effectively absorbed without being reflected or scattered” as disclosed by Lenchenkov throughout his disclosure and especially in ¶0031, ¶0034 and to have a layer “as an etching stop layer” as taught by Tsao.
Therefore, it would have been obvious to combine LEE, Lenchenkov and Tsao to obtain the invention as specified in claim 12.
Regarding Claim 13, LEE in view of Lenchenkov and Tso discloses wherein the contact etch stop layer comprises silicon nitride, carbon-doped silicon nitride, or a combination thereof (Tsao: Tsao in ¶0025 teach that the etching stop layer 160 is made of silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbon or another applicable material.).
Regarding Claim 14, LEE in view of Lenchenkov discloses wherein the depositing of the contact etch stop layer comprises depositing the contact etch stop layer by chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, or molecular layer deposition (In ¶0020 Tsao teaches that deposition process such as chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), a spin coating process or another applicable process could be used.).
Conclusion
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/PADMA HALIYUR/Primary Examiner, Art Unit 2639 September 22, 2026
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