Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
INFORMATION DISCLOSURE STATEMENT
The information disclosure statement filed 06/27/2025, has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-12 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 20200020684 in view of Chen et al. US 20210082874 hereinafter “Chen2”.
Consider claim 1 Chen discloses a chip stack structure fig. 1I [0010] 3DIC, comprising:
a first chip fig. 1I first die 100;
a second chip fig. 1I second die 200 over and bonded to the first chip through metal-to-metal bonding and dielectric-to-dielectric bonding fig. 1I see metal features 220 and 120 corresponding to conductive pads and bonding metal layers 122 and 222 and first and dielectric bonding layers 116 and 216, wherein the second chip has a first interconnect structure fig. 1I interconnect 204 and a first substrate over the first interconnect structure fig. 1I substrate 202,
an insulating layer fig. 1I layer 210 covering the first substrate fig. 1I 202 and covering the first interconnect structure fig. 1I 204; and
a conductive plug penetrating through the insulating layer to the first interconnect structure figs. 1H-1I see plug 224 226 with H2 and H3 penetrating 210 and 204.
Chen does not disclose an insulating layer surrounding the first substrate and covering the first interconnect structure.
Chen2 however discloses an insulating layer surrounding the first substrate and covering the first interconnect structure figs. 2B 4B, figs. 5-7 substrate 210 surrounded by insulation layer 400 and covering interconnect 220.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip stack structure of Chen to include an insulating layer surrounding the first substrate and covering the first interconnect structure, as taught by Chen2, to laterally encapsulate the dies 200 [0026-0027][0062].
Consider claim 2 Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 1, wherein the first interconnect structure comprises a wiring layer, and the conductive plug is connected to the wiring layer see Chen fig. 1H metal layer 108 connected to plug 224 226.
Consider claim 3. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 2, wherein the first interconnect structure comprises a first dielectric layer, the wiring layer is in the first dielectric layer [0014], a first surface of the wiring layer is exposed by the first dielectric layer, and the conductive plug is connected to the first surface of the wiring layer see Chen fig. 1A and 1H-1I [0014] interconnect 104 includes metal layer 108 and 106 which includes an inner layer dielectric and inter metal dielectric. Note 204 is the same as 104.
Consider claim 4. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 3, wherein the first surface of the wiring layer is substantially level with a second surface of the first dielectric layer under the first substrate see Chen 1H-1I the metal layer in the interconnect layer 204 is level with 210.
Consider claim 5. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 3, wherein the insulating layer extends into the first interconnect structure Chen2 disclose fig. 2K fig. 3, 5-7 see where 400 or 700 extending into the interconnect structure 620 or 220.
Motivation to combine is similar to motivation in claim 1.
Consider claim 6. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 5, wherein the conductive plug extends into the first interconnect structure Chen figs. 1H-1I see plug 224 226 with H2 and H3 penetrating 210 and 204.
Consider claim 7. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 6, wherein the first surface of the wiring layer is lower than a second surface of the first substrate, and the second surface faces the first interconnect structure Chen figs. 1I substrate 202 surface is above the metal layer of interconnect layer 204.
Consider claim 8. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 3 wherein the conductive plug has a first bottom surface lower than a top surface of the first dielectric layer and higher than a second bottom surface of the first dielectric layer Chen figs. 1I see end portion of 224 which protrudes into 204 the bottom surface of 204 is close to layer 203 and the top portion is close to 210.
Consider claim 9. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 3 wherein the first chip Chen figs. 1I first chip 100 comprises a second substrate Chen figs. 1I second substrate 102 and a second interconnect structure over the second substrate Chen figs. 1I second interconnect 104 ., and the second interconnect structure comprises a second dielectric layer Chen figs. 1I [0039]116 connected to the first dielectric layer of the first interconnect structure of the second chip Chen figs. 1I [0039]216 of die 200.
Consider claim 10. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 1, wherein the first chip comprises a second substrate and a second interconnect structure over the second substrate Chen figs. 1I first chip 100 second substrate 102 over second interconnect 104, the second interconnect structure comprises a second dielectric layer and a wiring layer in the second dielectric layer Chen figs. 1I fig. 1A [0014], and the conductive plug further penetrates through the first interconnect structure and extends into the first dielectric layer to be connected to the wiring layer figs. 1H-1I see plug 124 126 with H2 and H3 penetrating 110 and 104.
Consider claim 11. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 1, wherein a width of the conductive plug decreases toward the first chip Chen figs. 1I the plug 224 226 126 124 tapers upwards and downwards.
Claim 12 is rejected, mutatis mutandis, for similar reasons to claim 1 and claim 9.
Claim 14 is rejected, mutatis mutandis, for similar reasons to claim 1 and claim 9.
Claim 15 is rejected, mutatis mutandis, for similar reasons to claim 1 and claim 15.
Claim 15 is rejected, mutatis mutandis, for similar reasons to claim 1 and claim 15.
Consider claim 16. Chen as modified by Chen2 discloses the method for forming the chip stack structure as claimed in claim 14, further comprising: partially removing the second dielectric layer to form a trench in the second dielectric layer Chen2 fig. 2A, wherein the insulating layer is further formed in the trench Chen2 figs. 2B 4B, figs. 5-7 substrate 210 surrounded by insulation layer 400 and covering interconnect 220. and the conductive plug is partially in the second dielectric layer. Chen2 [0035] trenches and via holes are formed in the dielectric layer. fig. 2G 270 formed in the dielectric layer.
Consider claim 17. Chen as modified by Chen2 discloses the wherein the method for forming the chip stack structure as claimed in claim 14, wherein the forming of the conductive plug in the insulating layer Chen fig. 1G-1I. plug 124 formed in 110 or 224 in 224 comprises:
partially removing the insulating layer to form a through hole passing through the insulating layer and partially exposing a wiring layer of the second interconnect structure Chen fig. 1G-1H 108 of 104; and forming the conductive plug in the through hole Chen fig. 1H-1I.
Consider claim 18. Chen as modified by Chen2 discloses the method for forming the chip stack structure as claimed in claim 14, wherein the forming of the conductive plug in the insulating layer comprises:
partially removing the insulating layer and the second dielectric layer to form a through hole passing through the insulating layer and extending into the second dielectric layer and partially exposing a wiring layer of the second interconnect structure Chen fig. 1G-1I. plug 124 formed in 110 or 224 in 224 passing through 104 and metal layer 108; and forming the conductive plug in the through hole. Chen fig. 1H-1I.
Consider claim 19. Chen as modified by Chen2 discloses the method for forming the chip stack structure as claimed in claim 14, wherein the forming of the conductive plug in the insulating layer comprises: partially removing the insulating layer, the second dielectric layer, and the first dielectric layer Chen fig. 1G-1I. plug 124 formed in 110 or 224 in 224 passing through 104 and metal layer 108 to form a through hole passing through the insulating layer and the second dielectric layer and extending into the first dielectric layer and partially exposing a wiring layer of the first interconnect structure Chen fig. 1G-1I. plug 124 formed in 110 or 224 in 224 passing through 104 and metal layer 108; and forming the conductive plug in the through hole Chen fig. 1H-1I.
Consider claim 20. Chen as modified by Chen2 discloses the method for forming the chip stack structure as claimed in claim 14, wherein a first top surface of the second substrate structure, a second top surface of the insulating layer, and a third top surface of the conductive plug are substantially level with each other Chen2 fig. 2I 650 substrate 610 and insulation layer are level.
2. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 20200020684 in view of Chen et al. US 20210082874 hereinafter “Chen2” and further in view of Chen et al. US 20210375721 hereinafter “Chen3”.
Consider claim 13. Chen as modified by Chen2 discloses the chip stack structure as claimed in claim 12, but do not disclose wherein the conductive plug comprises a seed layer and a conductive pillar over the seed layer, and a second sidewall of the seed layer is substantially aligned with a third sidewall of the conductive pillar.
Chen3 however discloses wherein the conductive plug comprises a seed layer and a conductive pillar over the seed layer, and a second sidewall of the seed layer is substantially aligned with a third sidewall of the conductive pillar [0029] fig. 1E conductive via is formed by forming a seed layer over the insulating layer and in the opening via hole plating the conductive material over the seed layer. also see fig. 1H [0032] he filling process may be formed by, e.g., forming a seed layer in the via hole 170 and the line trench 162, plating (e.g., electroplating or electroless plating) the conductive material over the seed layer, and then removing the conductive material overfilling the line trench 162 by a planarization process such as CMP.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip stack structure of Chen as modified by Chen2 to include wherein the conductive plug comprises a seed layer and a conductive pillar over the seed layer, and a second sidewall of the seed layer is substantially aligned with a third sidewall of the conductive pillar, as taught by Chen2, to facilitate electroplating [0029].
III.CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 05/21/2026Primary Examiner, Art Unit 2628
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