Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on or before 2025-09-23 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,379,400 B2. Although the claims at issue are not identical, they are not patentably distinct from each other as indicated by the table below.
Instant application 19/523,779
US Patent #12,379,400 B2
Claim 1:
A die implementing an integrated circuit, comprising:
a substrate;
a plurality of electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit;
a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals; and
a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are disposed between different pairs of adjacent columns of the grid interconnect lands, wherein a first one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a first column of the grid of interconnect lands, and wherein a second one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a second column of the grid interconnect lands.
Claim 1:
A die implementing an integrated circuit, comprising:
a substrate;
a plurality of electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit;
a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals;
a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are disposed between different pairs of adjacent columns of the grid interconnect lands, wherein a first one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a first column of the grid of interconnect lands, and wherein a second one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a second column of the grid interconnect lands; and
a pair of resistive networks integrated on the die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments, wherein the resistors of the resistive networks have a first terminal electrically connected to the corresponding thin-film resistor segments at points along a width thereof and a second terminal electrically connected to a common sense node, and wherein the resistances of the resistive networks are scaled to compensate for the position of the electrical connections of the resistors of the resistive network along the width of the corresponding thin-film resistor segments.
Claim 2:
The die of Claim 1, wherein the at least two thin-film resistor segments extend substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die.
Claim 2:
The die of claim 1, wherein the at least two thin-film resistor segments extend substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die.
Claim 3:
The die of Claim 1, further comprising a metal interconnect disposed on the substrate that interconnects the first ends of the at least two thin-film resistor segments.
Claim 3:
The die of claim 1, further comprising a metal interconnect disposed on the substrate that interconnects the first ends of the at least two thin-film resistor segments.
Claim 4:
A die implementing an integrated circuit, comprising:
a substrate;
a plurality of electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit;
a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals; and
a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are disposed between different pairs of adjacent columns of the grid interconnect lands, wherein a first one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a first column of the grid of interconnect lands, and wherein a second one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a second column of the grid interconnect lands.
a pair of resistive networks integrated on the die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments at points along a width thereof.
Claim 1:
A die implementing an integrated circuit, comprising:
a substrate;
a plurality of electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit;
a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals;
a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are disposed between different pairs of adjacent columns of the grid interconnect lands, wherein a first one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a first column of the grid of interconnect lands, and wherein a second one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a second column of the grid interconnect lands; and
a pair of resistive networks integrated on the die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments,
wherein the resistors of the resistive networks have a first terminal electrically connected to the corresponding thin-film resistor segments at points along a width thereof and a second terminal electrically connected to a common sense node, and wherein the resistances of the resistive networks are scaled to compensate for the position of the electrical connections of the resistors of the resistive network along the width of the corresponding thin-film resistor segments.
Claim 5:
The die of Claim 1, wherein the first one of the at least two thin-film resistor segments is disposed between the first column and the second column of the grid interconnect lands, wherein the second one of the at least two thin-film resistor segments is disposed between a third column and a fourth column of the grid interconnect lands, and wherein the second column and the third column are adjacent.
Claim 5:
The die of claim 1, wherein the first one of the at least two thin-film resistor segments is disposed between the first column and the second column of the grid interconnect lands, wherein the second one of the at least two thin-film resistor segments is disposed between a third column and a fourth column of the grid interconnect lands, and wherein the second column and the third column are adjacent.
Claim 6:
The die of Claim 1, wherein the first one of the at least two thin-film resistor segments is disposed between the first column and the second column of the grid interconnect lands, wherein the second one of the at least two thin-film resistor segments is disposed between the second column and a third column of the grid interconnect lands, whereby the at least two thin-film resistor segments share a connection to the second column of grid interconnect lands.
Claim 6:
The die of claim 1, wherein the first one of the at least two thin-film resistor segments is disposed between the first column and the second column of the grid interconnect lands, wherein the second one of the at least two thin-film resistor segments is disposed between the second column and a third column of the grid interconnect lands, whereby the at least two thin-film resistor segments share a connection to the second column of grid interconnect lands.
Claim 7:
The die of Claim 1, wherein the at least two thin-film resistor segments have equal resistance.
Claim 7:
The die of claim 1, wherein the at least two thin-film resistor segments have equal resistance.
Claim 8:
The die of Claim 1, wherein the lands are solder ball lands.
Claim 8:
The die of claim 1, wherein the lands are solder ball lands.
Claim 9:
The die of Claim 1, wherein a resistance of the thin-film resistor is less than one ohm.
Claim 9:
The die of claim 1, wherein a resistance of the thin-film resistor is less than one ohm.
Claim 10:
The die of Claim 1, wherein thin-film resistor is formed by a tantalum nitride (TaN) layer.
Claim 10:
The die of claim 1, wherein thin-film resistor is formed by a tantalum nitride (TaN) layer.
Claim 11:
A method of fabricating an integrated circuit, comprising:
forming a plurality of electronic devices on a substrate of the integrated circuit and interconnecting the electronic devices to form at least a portion of an electronic circuit;
forming a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals;
depositing a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are deposited between different pairs of adjacent columns of the grid interconnect lands;
electrically connecting a first one of the at least two thin-film resistor segments along a width thereof to lands of a first column of the grid of interconnect lands; and
electrically connecting a second one of the at least two thin-film resistor segments along a width thereof to lands of a second column of the grid interconnect lands.
Claim 11:
A method of fabricating an integrated circuit, comprising:
forming a plurality of electronic devices on a substrate of the integrated circuit and interconnecting the electronic devices to form at least a portion of an electronic circuit;
forming a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals;
depositing a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are deposited between different pairs of adjacent columns of the grid interconnect lands;
electrically connecting a first one of the at least two thin-film resistor segments along a width thereof to lands of a first column of the grid of interconnect lands;
electrically connecting a second one of the at least two thin-film resistor segments along a width thereof to lands of a second column of the grid interconnect lands; and
forming a pair of resistive networks on a die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments, wherein the resistors of the resistive networks have a first terminal electrically connected to the corresponding thin-film resistor segments at points along a width thereof and a second terminal electrically connected to a common sense node, and wherein the resistances of the resistive networks are scaled to compensate for the position of the electrical connections of the resistors of the resistive network along the width of the corresponding thin-film resistor segments.
Claim 12:
The method of Claim 11, wherein the depositing deposits the at least two thin-film resistor segments substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die.
Claim 12:
The method of claim 11, wherein the depositing deposits the at least two thin-film resistor segments substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die.
Claim 13:
The method of Claim 11, further comprising forming a metal interconnect on the substrate that interconnects the first ends of the at least two thin-film resistor segments.
Claim 13:
The method of claim 11, further comprising forming a metal interconnect on the substrate that interconnects the first ends of the at least two thin-film resistor segments.
Claim 14:
(From Claim 11)
A method of fabricating an integrated circuit, comprising:
forming a plurality of electronic devices on a substrate of the integrated circuit and interconnecting the electronic devices to form at least a portion of an electronic circuit;
forming a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals;
depositing a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are deposited between different pairs of adjacent columns of the grid interconnect lands;
electrically connecting a first one of the at least two thin-film resistor segments along a width thereof to lands of a first column of the grid of interconnect lands; and
electrically connecting a second one of the at least two thin-film resistor segments along a width thereof to lands of a second column of the grid interconnect lands
(From Claim 12)
wherein the depositing deposits the at least two thin-film resistor segments substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die.
(From Claim 14)
further comprising forming a pair of resistive networks on the die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments at points along a width thereof.
Claim 14:
(From Claim 11)
A method of fabricating an integrated circuit, comprising:
forming a plurality of electronic devices on a substrate of the integrated circuit and interconnecting the electronic devices to form at least a portion of an electronic circuit;
forming a plurality of interconnect lands arranged in a grid for interconnecting the electronic devices with a plurality of external terminals;
depositing a thin-film resistor implemented by at least two thin-film resistor segments that are coupled in electrical parallel in the electronic circuit, wherein the at least two thin-film resistor segments are deposited between different pairs of adjacent columns of the grid interconnect lands;
electrically connecting a first one of the at least two thin-film resistor segments along a width thereof to lands of a first column of the grid of interconnect lands;
electrically connecting a second one of the at least two thin-film resistor segments along a width thereof to lands of a second column of the grid interconnect lands; and
(From Claim 12)
wherein the depositing deposits the at least two thin-film resistor segments substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die.
(From Claim 11)
forming a pair of resistive networks on a die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments, wherein the resistors of the resistive networks have a first terminal electrically connected to the corresponding thin-film resistor segments at points along a width thereof and a second terminal electrically connected to a common sense node, and wherein the resistances of the resistive networks are scaled to compensate for the position of the electrical connections of the resistors of the resistive network along the width of the corresponding thin-film resistor segments,
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9, 11-13, 15-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chintarlapalli et al. (US-20200303094-A1 – From IDS) in view of Tamagawa et al. (US-20140225220-A1 - From IDS).
Regarding Claim 1, Chintarlapalli teaches a die implementing an integrated circuit (Figs 1-n: integrated circuit layer, 100, 200, n00... where n is the figure number and Fig 11B: 1150), comprising:
a substrate (Figs 1-n: dielectric layer, 110, 210, 310, n10...);
a plurality of electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit (Fig 11B: Capacitors connected to TFR);
a plurality of interconnect lands arranged in a grid (Fig n: n30-1,2,3 etc. - these can be seen in Fig 11B, but are unlabeled) for interconnecting the electronic devices with a plurality of external terminals (Fig11B: IN,n1,n2,OUT etc.); and
a thin-film resistor implemented by at least two thin-film resistor segments (Refer to 1st Annotated Fig 11B of Chintarlapalli),
wherein the at least two thin-film resistor segments are disposed between different pairs of adjacent columns of the grid interconnect lands (Refer to 1st Annotated Fig 11B of Chintarlapalli),
wherein a first one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a first column (Refer to 1st Annotated Fig 11B of Chintarlapalli) of the grid of interconnect lands, and
wherein a second one of the at least two thin-film resistor segments is electrically connected along a width thereof to lands of a second column (Refer to 1st Annotated Fig 11B of Chintarlapalli) of the grid interconnect lands.
Chintarlapalli does not teach that the two thin-film resistor segments are coupled in electrical parallel in the electronic circuit. However, Tamagawa teaches coupling resistor segments in parallel (Para [0209] with reference to Fig 6, teaches connecting thin film resistor segments in parallel). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the thin film resistor segments of Chintarlapalli to be connected in electrical parallel as in Tamagawa. A Motivation for this modification is resistance units with small resistance values and low error among resistance values can be arranged as taught by Tamagawa in Para [0026].
Regarding Claim 2, the combination of Chintarlapalli in view of Tamagawa, as presented with respect to claim 1, teaches wherein the at least two thin-film resistor segments extend substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die (Tamagawa - Fig 16A shows thin film resistor element, 5, extending across the surface of the substrate, 2, such that one end of the thin film resistor is proximate a first edge and the other is proximate a second edge). These features are necessarily taught by the combination.
Regarding Claim 3, Chintarlapalli further teaches a metal interconnect disposed on the substrate that interconnects the first ends of the at least two thin-film resistor segments (Fig 11B: M).
Regarding Claim 5, Chintarlapalli further teaches wherein the first one of the at least two thin-film resistor segments is disposed between the first column and the second column of the grid interconnect lands, wherein the second one of the at least two thin-film resistor segments is disposed between a third column and a fourth column of the grid interconnect lands, and wherein the second column and the third column are adjacent (Can be seen in the 2nd annotated Figure 11B of Chintarlapalli).
Regarding Claim 6, Chintarlapalli further teaches wherein the first one of the at least two thin-film resistor segments is disposed between the first column and the second column of the grid interconnect lands, wherein the second one of the at least two thin-film resistor segments is disposed between the second column and a third column of the grid interconnect lands, whereby the at least two thin-film resistor segments share a connection to the second column of grid interconnect lands (Can be seen in the 3rd Annotated Figure 11B of Chintarlapalli).
Regarding Claim 7, Chintarlapalli further teaches wherein the at least two thin-film resistor segments have equal resistance (Para [0028] teaches that resistor segments that have substantially the same dimensions (length and width) will have the same resistance, the two resistor segments R8 and R9 shown in the 3rd annotated Figure 11B of Chintarlapalli are substantially the same size and therefore the same resistance).
Regarding Claim 9, Chintarlapalli in view of Tamagawa does not teach that the thin-film resistor is less than one ohm. However, Chintarlapalli does teach multiple values for thin-film resistors. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the value of the thin-film resistor to be less than 1 ohm as held in Aller; "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The motivation for doing so would be to achieve a particular current amount or voltage drop in the circuit, or as taught in Chintarlapalli, in order to achieve a desired footprint for the integrated circuit (see paragraphs [0003] through [0008]).
Regarding Claim 11, Chintarlapalli teaches a method of fabricating an integrated circuit, comprising:
forming a plurality of electronic devices on a substrate (Figs 1-n: dielectric layer, 110, 210, 310, n10...) of the integrated circuit and interconnecting the electronic devices to form at least a portion of an electronic circuit (Fig 11B: Capacitors connected to TFR);
forming a plurality of interconnect lands arranged in a grid (Fig n: n30-1,2,3 etc. - these can be seen in Fig 11B, but are unlabeled) for interconnecting the electronic devices with a plurality of external terminals (Fig11B: IN,n1,n2,OUT etc.);
depositing a thin-film resistor (Para [0026]) implemented by at least two thin-film resistor segments (Refer to 1st Annotated Fig 11B of Chintarlapalli),
wherein the at least two thin-film resistor segments are deposited between different pairs of adjacent columns of the grid interconnect lands (Refer to 1st Annotated Fig 11B of Chintarlapalli);
electrically connecting a first one of the at least two thin-film resistor segments along a width thereof to lands of a first column of the grid of interconnect lands (Refer to 1st Annotated Fig 11B of Chintarlapalli); and
electrically connecting a second one of the at least two thin-film resistor segments along a width thereof to lands of a second column of the grid interconnect lands (Refer to 1st Annotated Fig 11B of Chintarlapalli).
Chintarlapalli does not teach that the two thin-film resistor segments are coupled in electrical parallel in the electronic circuit. However, Tamagawa teaches coupling resistor segments in parallel (Para [0209] with reference to Fig 6, teaches connecting thin film resistor segments in parallel). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the thin film resistor segments of Chintarlapalli to be connected in electrical parallel as in Tamagawa. A Motivation for this modification is resistance units with small resistance values and low error among resistance values can be arranged as taught by Tamagawa in Para [0026].
Regarding Claim 12, the combination of Chintarlapalli in view of Tamagawa, as presented with respect to claim 1, teaches wherein the depositing deposits the at least two thin-film resistor segments substantially across the die, so that first ends of the at least two thin-film resistor segments are located proximate a first edge of the die, and so that second ends of the at least two thin-film resistor segments are located proximate a second edge of the die opposite the first edge of the die (Tamagawa - Fig 16A shows thin film resistor element, 5, extending across the surface of the substrate, 2, such that one end of the thin film resistor is proximate a first edge and the other is proximate a second edge.). These features are necessarily taught by the combination.
Regarding Claim 13, Chintarlapalli further teaches forming a metal interconnect on the substrate that interconnects the first ends of the at least two thin-film resistor segments (Fig 11B: M).
Regarding Claim 15, Chintarlapalli further teaches wherein the depositing deposits a first one of the at least two thin-film resistor segments between the first column and the second column of the grid interconnect lands, and wherein the depositing deposits the second one of the at least two thin- film resistor segments between a third column and a fourth column of the grid interconnect lands, wherein the second column and the third column are adjacent (Can be seen in the 2nd annotated Figure 11B of Chintarlapalli).
Regarding Claim 16, Chintarlapalli further teaches wherein the depositing deposits the first one of the at least two thin-film resistor segments between the first column and the second column of the grid interconnect lands, and wherein the depositing deposits the second one of the at least two thin- film resistor segments between the second column and a third column of the grid interconnect lands, whereby the at least two thin-film resistor segments share a connection to the second column of grid interconnect lands (Can be seen in the 3rd Annotated Figure 11B of Chintarlapalli).
Regarding Claim 17, Chintarlapalli further teaches wherein the at least two thin-film resistor segments have equal resistance (Para [0028] teaches that resistor segments that have substantially the same dimensions (length and width) will have the same resistance, the two resistor segments R8 and R9 shown in the 3rd annotated Figure 11B of Chintarlapalli are substantially the same size and therefore the same resistance).
Regarding Claim 19, Chintarlapalli in view of Tamagawa does not teach that the thin-film resistor is less than one ohm. However, Chintarlapalli does teach multiple values for thin-film resistors. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the value of the thin-film resistor to be less than 1 ohm as held in Aller; "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The motivation for doing so would be to achieve a particular current amount or voltage drop in the circuit, or as taught in Chintarlapalli, in order to achieve a desired footprint for the integrated circuit (see paragraphs [0003] through [0008]).
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1st Annotated Figure 11B of Chintarlapalli
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2nd Annotated Figure 11B of Chintarlapalli
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3rd Annotated Figure 11B of Chintarlapalli
Claims 4, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chintarlapalli in view of Tamagawa in view of Holland et al. (US-20210364560-A1 – From IDS).
Regarding Claim 4, the combination of Chintarlapalli in view of Tamagawa teaches at least two thin film resistor segments (Refer to 1st Annotated Fig 11B of Chintarlapalli). The combination does not teach a pair of resistive networks integrated on the die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments at points along a width thereof. However, Holland teaches a pair of resistive networks integrated on the die (Fig 1: Passive Combination Network, 100 | Fig 4 shows and example of a passive combination network), wherein the resistive networks are electrically connected to a thin-film resistor segment at points along a width thereof (Can be seen in Fig 1, Passive combination networks, 100, connect to resistor network, 106). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination to incorporate the resistive networks of Holland. A motivation for this modification is to allow for a plurality of points along thing film resistor to be combined into a single sense point as taught by Holland (Abstract).
Regarding Claim 14, the combination of Chintarlapalli in view of Tamagawa teaches at least two thin film resistor segments (Refer to 1st Annotated Fig 11B of Chintarlapalli). The combination does not teach forming a pair of resistive networks on the die, wherein the resistive networks are electrically connected to a corresponding one of the at least two thin-film resistor segments at points along a width thereof. However, Holland teaches forming a pair of resistive networks on the die (Fig 1: Passive Combination Network, 100 | Fig 4 shows and example of a passive combination network), wherein the resistive networks are electrically connected to a thin-film resistor segment at points along a width thereof (Can be seen in Fig 1, Passive combination networks, 100, connect to resistor network, 106). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination to incorporate the resistive networks of Holland. A motivation for this modification is to allow for a plurality of points along thing film resistor to be combined into a single sense point as taught by Holland (Abstract).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chintarlapalli in view of Tamagawa in view of Abraham et al. (US-10727192-B2 – From IDS).
Regarding Claims 8 and 18, the combination of Chintarlapalli in view of Tamagawa does not teach that the lands are solder ball lands. However, Abraham teaches solder ball lands (Fig 3: 22a). Therefore, it would have been obvious to someone of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the lands taught by the combination to be solder balls as taught by Abraham. The motivation for this modification is that solder ball lands are used in C4 (Controlled-Collapse Chip Connection) which is a means of connecting semiconductor chips to substrates in electronic packages where the interconnections are small solder balls (bumps) on the chip surface. Since the solder balls forms an area array, C4 technology has the advantage of achieving the highest density of interconnection to the device with the lowest parasitic inductance as taught by Abraham (column 3, lines 41-50).
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chintarlapalli in view of Tamagawa in view of Lee (NPL - “Characterization and Reliability of TaN Thin Film Resistors” – From IDS).
Regarding Claims 10 and 20, the combination of Chintarlapalli in view of Tamagawa does not teach a thin-film resistor is formed by a tantalum nitride (TaN) layer. However, Lee teaches a thin-film resistor is formed by a tantalum nitride layer (Abstract). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the thin-film resistors taught by the combination to be made of TaN as taught by Lee. The motivation for doing so is that TaN film may be well controlled to produce a high precision resistor, and the temperature coefficient of resistance (TCR) characteristics of the film make it ideally suited for application across a large temperature range as taught by Lee (See Abstract).
Conclusion
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/JEREMIAH J BARRON/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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