DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al. (US 2013/0257846) in view of Teranishi (US 2011/0316897).
As to Claim 1, Matsuda et al. discloses A liquid crystal display device comprising: a pixel including a first memory circuit (fig.2-4; data retention section DS1; para.0061,0073; fig.11,14), a second memory circuit (fig.2-4; data retention section DS2; para.0061,0075), and a display circuit including a liquid crystal capacitance and connected to the first memory circuit and the second memory circuit (fig.4, liquid crystal capacitor Clc, para.0110);
a first power source line and a second power source line each connected to the display circuit
a refresh circuit configured to read memory data stored in the first memory circuit and write back the memory data to the first memory circuit in accordance with a result of the reading (figs.2-4; para.0083, 0087-0089,0093-0094,0096; first data retention section DS1 transfers binary logic level to second data retention DS2, which in turn provides control information to the refresh output control section RS1 indicating the first electric potential is being retained in DS2, the refresh output section RS1 then writes a second electric potential level over the binary logic that has been retained until then in retention data section DS1); and
a control circuit configured to control the refresh circuit (fig.2-4; refresh output control line RC1 controls the refresh output section RS1; para.0087,0090).
Matsuda et al. does not expressly disclose a first power source line and a second power source line each connected to the display circuit ; a refresh circuit configured to read memory data stored in the first memory circuit.
Teranishi discloses a pixel comprising a first power source line and a second power source line each connected to the display circuit (fig.3-4, potential Vsig/Vxcs, Vdd, and Vss; para.0128-129); a refresh circuit configured to read memory data stored in the first memory circuit (fig.4, transistors 24-27 and inverter 23 collectively; para.0114,0116-0120,0123-0125; the held potential of holding capacitance 22 is read out and provided to the inverter 23, the inverter then inverts the polarity of the held potential, and inverted potential is then written to the holding capacitance 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Matsuda et al., with the teachings of Teranishi, the motivation being to provide a refresh operation enabling performance enhancement such as power consumption reduction and improvement in the operating margin of DRAM.
As to Claim 2, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit writes back inverted data of the memory data read from the first memory circuit to the first memory circuit (Matsuda-figs.2-4,11,14; para.0093-0094,0096; Teranishi-figs.3-4-para. 0123-0125).
As to Claim 3, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit writes back the same data as the memory data read from the first memory circuit to the second memory circuit (Matsuda-figs.2-4; para.0074,0083- binary logic level retained in data retention section DS1 is transferred to second data retention section DS2).
As to Claim 4, Matsuda et al. in view of Teranishi disclose wherein potentials of the first power source line and the second power source line are exchanged to each other in accordance with the writing-back (Matsuda-para.0218; Teranishi- para.0266; fig.11).
As to Claim 5, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit receives an instruction from the control circuit and performs the writing-back within a memory maintaining period of the first memory circuit (Matsuda-para.0116, 0121- period t6 refresh output is high within memory period MRY).
As to Claim 6, Matsuda et al. in view of Teranishi disclose wherein the control circuit includes a timer and a timing controller, and the timing controller activated by the timer controls the refresh circuit (Matsuda-fig.1, para.0064; Teranishi-fig.1, para.0106,0150)).
As to Claim 7, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit stops after the writing-back (Matsuda-para.0093; Ternanishi-para.0227,0229,0231)
As to Claim 8, Matsuda et al. in view of Teranishi do not expressly disclose wherein the timing controller stops after the writing-back. However, in Matsuda et al. in view of Teranishi, Teranishi discloses where during a rewriting operation switch elements 27 and 25 are in on state, and where the timing generator 60 controls the on/off states of the switch elements 24-27 (para.0121, 0124,0156). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device as disclosed by Matsuda et al. in view of Teranishi, such that the timing control 60 stops the switch elements 27,25 after rewriting operation is performed. The motivation being to aid in reduction in the power consumption of the deivce.
As to Claim 9, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit includes a reading circuit configured to read memory data and a latch circuit configured to latch the read memory data (Teranishi- fig.3-4,15 para.0123-0125; 0269-0270; transistors 25-26 are on state, during which the capacitance is read out and sent to the inverter circuit 23, where the inverter may have a latch configuration).
As to Claim 20, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit reads memory data stored in the second memory circuit, and notifies the timing controller when the memory data stored in the first memory circuit and the memory data stored in the second memory circuit are not in an inverted relationship (para.0088, RS1 is brought into active state, and refresh operation is performed; para.0064,0076- driving signal generating circuit controls memory operation).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al. (US 2013/0257846) in view of Teranishi (US 2011/0316897), further in view of Tobita et al. (US 20020180675).
As to Claim 23, Matsuda et al. in view of Teranishi disclose a display region in which a pixel group including the pixel is provided (Matsuda-fig.1; Teranishi-fig.1).
Matsuda et al. in view of Teranishi do not expressly disclose a non-display region in which the refresh circuit is provided.
Tobita et al. discloses a non-display region in which the refresh circuit is provided (fig.1-2, refresh circuit 6 separate from the pixel area 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Matsuda et al. in view of Teranishi, with the teachings of Tobita et al. with the teachings of Tobita et al., the motivation being to provide the refresh circuit in area separate from the pixel matrix.
Allowable Subject Matter
Claims 10-19, 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest: a first data line connected to the first memory circuit; and a second data line connected to the second memory circuit, wherein the display circuit includes a first transistor connected to the first memory circuit and a second transistor connected to the second memory circuit, the liquid crystal capacitance includes a pixel electrode and a counter electrode, and the pixel electrode is connected to the first power source line via the first transistor and is connected to the second power source line via the second transistor, in combination with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892 form.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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