DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-8 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2022/0302240 A1, hereinafter referred as “Zhang”).
Regarding claim 1, Zhang discloses a display apparatus (title and abstract discloses display panel) comprising:
a substrate (10) comprising a display region (AA) (Figs. 1, 4-7, 10-12, ¶0054 and ¶0058 discloses the display panel including base substrate 10 may include a display area AA) and a non-display region (BB) surrounding the display region (AA) (Figs. 1, 4-7, 10-12, ¶0054 and ¶0061 the display panel including base substrate 10 further includes a non-display area BB around the display area AA); and
a gate driving circuit (13, 14) in the non-display region (BB) of the substrate (10) (Fig. 1, ¶0061, ¶0085 and ¶0126 discloses a scanning driving circuit 13 and a light-emitting control circuit 14 which are located in the non-display area BB of the base substrate 10) and comprising a plurality of stages (¶0064 discloses the light-emitting control circuit 14 may include: a plurality of cascaded first shifting registers; and ¶0112 discloses the scanning driving circuit 13 may include: a plurality of cascaded second shifting registers),
wherein each of the plurality of stages comprises a peripheral oxide transistor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 of the light emitting control circuit 14 and scanning driving circuit 13 are made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials), comprising a first semiconductor layer comprising an oxide semiconductor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 may be made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials), and a peripheral silicon transistor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 of the light emitting control circuit 14 and scanning driving circuit 13 are made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials), comprising a second semiconductor layer comprising a silicon semiconductor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 may be made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials),
the peripheral oxide transistor further comprises a first lower gate electrode under the first semiconductor layer (500) (Figs. 4-5, 11, ¶0083 and ¶0085 discloses light-emitting control transistors T1-T12 may include first bottom gates located under the semiconductor layer 500, and ¶0124 scanning driving transistors T13-T20 may include second bottom gates located under the semiconductor layer 500) and a first upper gate electrode above the first semiconductor layer (500) (Figs. 4-5, 11, ¶0083 and ¶0085 discloses light-emitting control transistors T1-T12 includes first top gates located above the semiconductor layer 500, and ¶0124 discloses the scanning driving transistors T13-T20 may include second top gates located above the semiconductor layer 500), and
the first lower gate electrode and the first upper gate electrode are electrically connected to each other (¶0083 discloses the light-emitting control transistors T1-T12 may include first bottom gates and first top gates which are electrically connected with each other; and ¶0124 discloses scanning driving transistors T13-T20 may include second bottom gates and second top gates which are electrically connected to each other).
Regarding claim 2, Zhang discloses the display apparatus of claim 1, wherein each of the plurality of stages further comprises a first connection electrode that connects the first lower gate electrode to the first upper gate electrode (Fig. 2 and ¶0083 discloses the light-emitting control transistors T1-T12 may include first bottom gates and first top gates which are electrically connected with each other; and Fig. 8 and ¶0124 discloses scanning driving transistors T13-T20 may include second bottom gates and second top gates which are electrically connected to each other).
Regarding claim 3, Zhang discloses the display apparatus of claim 2, wherein the first connection electrode is on the first upper gate electrode (Figs. 4, 5 and 11 illustrate connection electrode contacting the top gate electrodes T8-G1, T6-G1 and T16-G1), and the first connection electrode is connected to each of the first lower gate electrode and the first upper gate electrode via a contact hole (Figs. 4, 5 and 11 illustrate connection electrode connecting the top gate electrodes T8-G1, T6-G1 and T16-G1 to the bottom gate electrodes T8-L1, T6-L1 and T16-L1, respectively, via a contact hole).
Regarding claim 4, Zhang discloses the display apparatus of claim 2, wherein the peripheral silicon transistor (Fig. 1, 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 of the light emitting control circuit 14 and scanning driving circuit 13 are made of amorphous silicon, and polycrystalline silicon)) further comprises a second lower gate electrode under the second semiconductor layer (Figs. 4-5, 11, ¶0083 and ¶0085 discloses light-emitting control transistors T1-T12 may include first bottom gates located under the semiconductor layer 500, and ¶0124 scanning driving transistors T13-T20 may include second bottom gates located under the semiconductor layer 500), and a second upper gate electrode above the second semiconductor layer (Figs. 4-5, 11, ¶0083 and ¶0085 discloses light-emitting control transistors T1-T12 includes first top gates located above the semiconductor layer 500, and ¶0124 discloses the scanning driving transistors T13-T20 may include second top gates located above the semiconductor layer 500).
Regarding claim 5, Zhang discloses the display apparatus of claim 4, wherein the second lower gate electrode is electrically connected to the second upper gate electrode (¶0083 discloses the light-emitting control transistors T1-T12 may include first bottom gates and first top gates which are electrically connected with each other; and ¶0124 discloses scanning driving transistors T13-T20 may include second bottom gates and second top gates which are electrically connected to each other).
Regarding claim 6, Zhang discloses the display apparatus of claim 5, wherein each of the plurality of stages further comprises a second connection electrode that connects the second lower gate electrode to the second upper gate electrode (Fig. 2 and ¶0083 discloses the light-emitting control transistors T1-T12 may include first bottom gates and first top gates which are electrically connected with each other; and Fig. 8 and ¶0124 discloses scanning driving transistors T13-T20 may include second bottom gates and second top gates which are electrically connected to each other).
Regarding claim 7, Zhang discloses the display apparatus of claim 6, wherein the first connection electrode and the second connection electrode are on a same layer (Figs. 4, 5 and 11 illustrate connection electrode connecting the top gate electrodes T8-G1, T6-G1 and T16-G1 to the bottom gate electrodes T8-L1, T6-L1 and T16-L1, respectively are on the same layer).
Regarding claim 8, Zhang discloses the display apparatus of claim 4, wherein the second semiconductor layer comprises a channel region, a source region on one side of the channel region, and a drain region on the other side of the channel region (¶0088 discloses all the active layers may include source electrode regions, drain electrode regions and channel regions between the source electrode regions and the drain electrode regions), and the second lower gate electrode is electrically connected to the source region of the second semiconductor layer (Figs. 4-5 illustrate the bottom gate electrodes T6-L1 and T8-L1 partially overlapping the semiconductor layer 500 which also suggests an electrical interaction between the two layers).
Regarding claim 20, Zhang discloses an electronic apparatus (¶0003 discloses display panels may be configured in various intelligent terminals such as mobile phones, tablet computers, televisions, smart wearables) comprising a display apparatus (title and abstract discloses display panel) comprising:
a substrate (10) comprising a display region (AA) (Figs. 1, 4-7, 10-12, ¶0054 and ¶0058 discloses the display panel including base substrate 10 may include a display area AA) and a non-display region (BB) surrounding the display region (AA) (Figs. 1, 4-7, 10-12, ¶0054 and ¶0061 the display panel including base substrate 10 further includes a non-display area BB around the display area AA); and
a gate driving circuit (13, 14) in the non-display region (BB) of the substrate (10) (Fig. 1, ¶0061, ¶0085 and ¶0126 discloses a scanning driving circuit 13 and a light-emitting control circuit 14 which are located in the non-display area BB of the base substrate 10) and comprising a plurality of stages (¶0064 discloses the light-emitting control circuit 14 may include: a plurality of cascaded first shifting registers; and ¶0112 discloses the scanning driving circuit 13 may include: a plurality of cascaded second shifting registers),
wherein each of the plurality of stages comprises a peripheral oxide transistor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 of the light emitting control circuit 14 and scanning driving circuit 13 are made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials), comprising a first semiconductor layer comprising an oxide semiconductor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 may be made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials), and a peripheral silicon transistor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 of the light emitting control circuit 14 and scanning driving circuit 13 are made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials), comprising a second semiconductor layer comprising a silicon semiconductor (Figs. 4-7, 10-12, ¶0085, ¶0088 and ¶0126 discloses the active semiconductor layer 500 may be made of amorphous silicon, polycrystalline silicon and oxide semiconductor materials),
the peripheral oxide transistor further comprises a first lower gate electrode under the first semiconductor layer (500) (Figs. 4-5, 11, ¶0083 and ¶0085 discloses light-emitting control transistors T1-T12 may include first bottom gates located under the semiconductor layer 500, and ¶0124 scanning driving transistors T13-T20 may include second bottom gates located under the semiconductor layer 500) and a first upper gate electrode above the first semiconductor layer (500) (Figs. 4-5, 11, ¶0083 and ¶0085 discloses light-emitting control transistors T1-T12 includes first top gates located above the semiconductor layer 500, and ¶0124 discloses the scanning driving transistors T13-T20 may include second top gates located above the semiconductor layer 500), and
the first lower gate electrode and the first upper gate electrode are electrically connected to each other (¶0083 discloses the light-emitting control transistors T1-T12 may include first bottom gates and first top gates which are electrically connected with each other, and ¶0124 discloses scanning driving transistors T13-T20 may include second bottom gates and second top gates which are electrically connected to each other).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 9-10 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Osawa et al. (US 2015/0055051 A1, hereinafter referred as “Osawa”).
Regarding claim 9, Zhang doesn’t disclose the display apparatus of claim 4, wherein the first semiconductor layer and the second semiconductor layer are on different layers.
However, in the same field of endeavor, Osawa discloses wherein the first semiconductor layer (204) and the second semiconductor layer (224) are on different layers (Fig. 7 and ¶0054 discloses the semiconducting oxide layer 224 and the polysilicon layer 204 are deposited on different layers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang for the purpose of improving layout density and routing freedom.
Regarding claim 10, Zhang doesn’t explicitly disclose the display apparatus of claim 9, wherein the second upper gate electrode is under the first lower gate electrode.
However, Zhang discloses the semiconducting layer 500 intervenes the top and bottom gate electrodes. See Figs. 4, 5 and 11 of Zhang. Osawa as modified by Zhang discloses a top gate 218 stacked on top of the semiconductor layer 204 and a bottom gate formed below the semiconductor layer 204 of transistor 216, and a top gate formed above the semiconductor layer 224 and a bottom gate 228’ formed below the semiconductor layer 224. See Fig. 7 of Osawa. The combination of Zhang in view of Osawa yields the top gate 218 of transistor 216 formed in a layer below the bottom gate 228’ of transistor 240. See Fig. 7 of Osawa.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang for the purpose of maintaining switching speeds in silicon transistors and low leakage current in oxide transistors (¶0034).
Regarding claim 13, Zhang discloses the display apparatus of claim 1, further comprising: a pixel circuit (0121) in the display region (AA) (Figs. 1, 13, ¶0058 and ¶0143 discloses display area AA may include a plurality of pixel units PX each comprising a pixel circuit 0121); and a light-emitting diode (0120) electrically connected to the pixel circuit (0121) (Fig. 13 illustrates pixel circuit 0121 connected to a light-emitting element 0120)…
Zhang doesn’t disclose a pixel circuit [on] the substrate; wherein the pixel circuit comprises a main oxide transistor, comprising a third semiconductor layer comprising an oxide semiconductor, and a main silicon transistor, comprising a fourth semiconductor layer comprising a silicon semiconductor, the main oxide transistor further comprises a third lower gate electrode under the third semiconductor layer and a third upper gate electrode above the third semiconductor layer, and the third semiconductor layer and the fourth semiconductor layer are on different layers.
However, in the same field of endeavor, Osawa discloses a pixel circuit [on] the substrate (24) (Figs. 1-3, ¶0081 and claim 1 discloses array of display pixels including pixel circuitry on the substrate); wherein the pixel circuit comprises a main oxide transistor, comprising a third semiconductor layer comprising an oxide semiconductor (¶0034 discloses oxide transistors (e.g., IGZO transistors) may be used where low leakage current is desired (e.g., in liquid crystal diode display pixels and display driver circuitry)), and a main silicon transistor, comprising a fourth semiconductor layer comprising a silicon semiconductor (¶0034 discloses silicon transistors (e.g., LTPS transistors) may be used where attributes such as switching speed and good drive current are desired (e.g., for gate drivers in liquid crystal diode displays or in portions of an organic light-emitting diode display pixel where switching speed is a consideration)), the main oxide transistor (240) further comprises a third lower gate electrode (228’) under the third semiconductor layer (224) and a third upper gate electrode above the third semiconductor layer (224) (combination of Zhang and Osawa discloses a top gate formed above the semiconductor layer 224, since Zhang discloses the semiconducting layer 500 intervenes the top and bottom gate electrodes), and the third semiconductor layer (224) and the fourth semiconductor layer (204) are on different layers (Fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang for the purpose of maintaining switching speeds in silicon transistors and low leakage current in oxide transistors (¶0034).
Regarding claim 14, Zhang discloses the display apparatus of claim 13, wherein the pixel circuit further comprises a third connection electrode that electrically connects the third lower gate electrode to the third upper gate electrode (¶0083 discloses the light-emitting control transistors T1-T12 may include first bottom gates and first top gates which are electrically connected with each other; and ¶0124 discloses scanning driving transistors T13-T20 may include second bottom gates and second top gates which are electrically connected to each other).
6. Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Kim et al. (US 2023/0206853 A1, hereinafter referred as “Kim6853”) and in further view of Park et al. (US 2022/0172659 A1, hereinafter referred as “Park”).
Regarding claim 11, Zhang doesn’t disclose the display apparatus of claim 1, wherein the peripheral silicon transistor further comprises: a first peripheral transistor connected between a first terminal, to which a start signal is input, and a first node, and comprising a gate connected to a clock terminal configured to receive a clock signal; a second peripheral transistor connected between a second terminal configured to receive a first voltage, and a second node, and comprising a gate connected to the first node; a third peripheral transistor connected between the first node and a third node and comprising a gate connected to a third terminal configured to receive a second voltage lower than the first voltage; a fourth peripheral transistor connected between the second terminal and an output terminal and comprising a gate connected to the second node; and a fifth peripheral transistor connected between the output terminal and the third terminal and comprising a gate connected to the third node, and the peripheral oxide transistor further comprises a sixth peripheral transistor connected between the second node and the third terminal and comprising a gate connected to the third node.
However, in the same field of endeavor, Kim6853 discloses wherein the peripheral silicon transistor (Figs. 1, 3-4 and ¶0081 discloses stage of a gate driver 120 including transistors that are p-type low-temperature polysilicon transistors) further comprises: a first peripheral transistor (T3) connected between a first terminal, to which a start signal is input (SCAN1(n-1)), and a first node (Q2), and comprising a gate connected to a clock terminal configured to receive a clock signal (LCLK1) (Fig. 4); a second peripheral transistor (T5) connected between a second terminal configured to receive a first voltage (VGH), and a second node (QB), and comprising a gate connected to the first node (Q2); a third peripheral transistor (Ta1) connected between the first node (Q2) and a third node (Q)…; a fourth peripheral transistor (T2) connected between the second terminal (VGH) and an output terminal (SCAN1(n)) and comprising a gate connected to the second node (QB); and a fifth peripheral transistor (T1) connected between the output terminal (SCAN1(n)) and the third terminal (VGL2) and comprising a gate connected to the third node (Q), and the peripheral oxide transistor (Figs. 1, 3-4 and ¶0081 discloses the fourth transistor T4 among the plurality of transistors of the stage ST(n) of a gate driver 120 is an n-type oxide semiconductor transistor) further comprises a sixth peripheral transistor (T4) connected between the second node (QB) and the third terminal (VGL2) and comprising a gate connected to the third node (Q) (Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang for the purpose of improving noise immunity by reducing false triggers from clock feedthrough, coupling, or leakage.
Zhang as modified doesn’t disclose a third peripheral transistor… comprising a gate connected to a third terminal configured to receive a second voltage.
However, in the same field of endeavor, Park discloses a third peripheral transistor (T2)… comprising a gate connected to a third terminal configured to receive a second voltage (VGL) (Fig. 3 and ¶0080 discloses the second transistor T2 may be controlled by a low level voltage VGL).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang for the purpose of reducing the number of inputs of the scan driving circuit.
Regarding claim 12, Zhang discloses the display apparatus of claim 11, wherein each of the plurality of stages further comprises: a first capacitor (C1) connected between the output terminal (U4) and the third node (PD_out); and a second capacitor (C2) connected between the second terminal (VGH) and the second node (PU) (Fig. 2).
7. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Osawa, and in further view of Kwak et al. (US 2021/0036087 A1, hereinafter referred as “Kwak”).
Regarding claim 15, Zhang as modified doesn’t disclose the display apparatus of claim 13, wherein the main silicon transistor further comprises: a first main transistor connected between a driving voltage line and the light-emitting diode and configured to control a current supplied to the light-emitting diode; a second main transistor connected between a data line and a first main node connected to a first terminal of the first main transistor; a third main transistor connected between the driving voltage line and the first main node; and a fourth main transistor connected between the first main transistor and the light-emitting diode, and the main oxide transistor further comprises: a fifth main transistor connected between a second main node connected to a gate of the first main transistor and a third main node connected to a second terminal of the first main transistor; and a sixth main transistor connected between a first initialization voltage line and the second main node.
However, in the same field of endeavor, Kwak discloses wherein the main silicon transistor (Fig. 3 and ¶0097 discloses at least one of the other remaining ones of the plurality of transistors T1 to T7 may include a semiconductor layer including silicon) further comprises: a first main transistor (T1) connected between a driving voltage line (PL) and the light-emitting diode (OLED) and configured to control a current supplied to the light-emitting diode (Fig. 3 and ¶0088 discloses form a current path (e.g., with the first transistor T1) on which the driving current IOLED may flow from the power voltage line PL in a direction toward the organic light-emitting diode OLED); a second main transistor (T2) connected between a data line (DATA) and a first main node connected to a first terminal of the first main transistor (T1) (Fig. 3 and ¶0084 discloses the first transistor T1 may receive a signal corresponding to data signal DATA according to a switching operation of the second transistor T2); a third main transistor (T5) connected between the driving voltage line (PL) and the first main node (Fig. 3 and ¶0084 discloses first transistor T1 may be connected to the power voltage line PL via the fifth transistor T5); and a fourth main transistor (T6) connected between the first main transistor (T1) and the light-emitting diode (OLED) (Fig. 3 and ¶0084 discloses the first transistor T1… may be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6), and the main oxide transistor (¶0097 discloses at least one of the plurality of transistors T1 to T7 includes a semiconductor layer including an oxide) further comprises: a fifth main transistor (T3) connected between a second main node (N) connected to a gate of the first main transistor (T1) and a third main node connected to a second terminal of the first main transistor (T1) (Fig. 3 and ¶0084-¶0086 discloses the third transistor T3 connected between node N and the second terminal of first transistor T1); and a sixth main transistor (T4) connected between a first initialization voltage line (Vint) and the second main node (N) (Fig. 3 and ¶0087 discloses the fourth transistor T4 may transmit the initialization voltage Vint from the initialization voltage line VIL to a gate electrode of the first transistor T1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang for the purpose of maintaining switching speeds in silicon transistors and low leakage current in oxide transistors.
8. Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Osawa, in further view of Kwak and still in further view of Kim et al. (US 2023/0157071 A1, hereinafter referred as “Kim7071”).
Regarding claim 16, Zhang as modified doesn’t disclose the display apparatus of claim 15, wherein each of the fifth main transistor and the sixth main transistor comprises a structure in which the third lower gate electrode and the third upper gate electrode are electrically connected to each other.
However, in the same field of endeavor, Kim7071 discloses wherein each of the fifth main transistor (T3) and the sixth main transistor (T4) comprises a structure in which the third lower gate electrode and the third upper gate electrode are electrically connected to each other (Fig. 3B and ¶0093 discloses gates G3-1 and G3-2 of the third transistor T3 may be electrically connected, and ¶0094 discloses gates G4-1 and G4-2 of the fourth transistor T4 may be electrically connected).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang for the purpose of having more electrostatic control of the channel than a single-gate TFT.
Regarding claim 17, Zhang as modified doesn’t disclose the display apparatus of claim 15, wherein the pixel circuit further comprises a first main capacitor connected between the driving voltage line and the second main node, and the main silicon transistor further comprises a seventh main transistor connected between a second initialization voltage line and the light-emitting diode.
However, in the same field of endeavor, Kim7071 discloses wherein the pixel circuit (PXij) further comprises a first main capacitor (Cst) connected between the driving voltage line (ELVDD) and the second main node (RN) (Fig. 3B and ¶0089 discloses capacitor Cst may be connected between the first voltage line PL (which receives the first power supply voltage ELVDD) and a reference node RN), and the main silicon transistor further comprises a seventh main transistor (T7) (Fig. 3B and ¶0088 discloses the seventh transistor T7 may each be a silicon transistor) connected between a second initialization voltage line (VAint) and the light-emitting diode (LD) (Fig. 3B, ¶0083 and ¶0098 discloses seventh transistor T7 may be electrically connected between the drain D6 of the sixth transistor T6 and the third voltage line VL2 which receives a second initialization voltage VAint).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang so that the anode of the light emitting element LD may be initialized to the second initialization voltage VAint (¶0104).
9. Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Osawa, in further view of Kim et al. (US 2024/0107812 A1, hereinafter referred as “Kim7812”) and still in further view of Choi et al. (US 2023/0337470 A1, hereinafter referred as “Choi”).
Regarding claim 18, Zhang as modified doesn’t disclose the display apparatus of claim 13, wherein the main oxide transistor further comprises: a first main transistor connected between a driving voltage line and the light-emitting diode and configured to control a current supplied to the light-emitting diode; a second main transistor connected between a data line and a first main node connected to a gate of the first main transistor; a third main transistor connected between a reference voltage line and the first main node; and a fourth main transistor connected between an initialization voltage line and the light-emitting diode, and the main silicon transistor further comprises: a fifth main transistor connected between the driving voltage line and the first main transistor; and a sixth main transistor connected between a second main node connected to a first terminal of the first main transistor and the light-emitting diode, wherein at least one of the first main transistor, the second main transistor, the third main transistor, or the fourth main transistor has a structure in which the third lower gate electrode and the third upper gate electrode are electrically connected to each other.
However, in the same field of endeavor, Kim7812 discloses wherein the main oxide transistor (¶0065 discloses all transistors (T1, T2, T3, T4, and T5) are formed of n-type transistors, and an oxide semiconductor is used as the semiconductor layer) further comprises: a first main transistor (T1) connected between a driving voltage line (ELVDD) and the light-emitting diode (LED) and configured to control a current supplied to the light-emitting diode (LED) (Fig. 1 and ¶0059 discloses a first electrode of the driving transistor T1 is disposed to receive the driving voltage ELVDD, and is connected to the driving voltage line 172 via the fifth transistor T5. Meanwhile, a second electrode of the driving transistor T1 outputs the light emitting current to the light emitting diode LED); a second main transistor (T2) connected between a data line (171) and a first main node connected to a gate of the first main transistor (T1) (Fig. 1 and ¶0060 discloses first electrode of the second transistor T2 is connected to data line 171, and a second electrode of the second transistor T2 is connected to the driving gate electrode of the driving transistor T); a third main transistor (T3) connected between a reference voltage line (127) and the first main node (Fig. 1 and ¶0061 discloses third transistor T3 serves to transmit the reference voltage Vref to the driving gate electrode of the driving transistor T1); and a fourth main transistor (T4) connected between an initialization voltage line (128) (Fig. 1 and ¶0062 discloses the first electrode of the fourth transistor T4 is connected to the initialization voltage line 128) and the light-emitting diode (LED) (Fig. 1 and ¶0062 discloses second electrode of the fourth transistor T4 is connected one electrode of the light emitting diode LED), and the main silicon transistor (¶0065 discloses all transistors (T1, T2, T3, T4, and T5) are formed of n-type transistors and a silicon semiconductor may also be used for the semiconductor layer) further comprises: a fifth main transistor (T5) connected between the driving voltage line (172) and the first main transistor (T1) (Fig. 1 and ¶0063 discloses fifth transistor T5 serves to transmit the driving voltage ELVDD to the first electrode of the driving transistor T1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang for the purpose of maintaining switching speeds in silicon transistors and low leakage current in oxide transistors.
Zhang as modified still doesn’t disclose the main silicon transistor further comprises: a sixth main transistor connected between a second main node connected to a first terminal of the first main transistor and the light-emitting diode, wherein at least one of the first main transistor, the second main transistor, the third main transistor, or the fourth main transistor has a structure in which the third lower gate electrode and the third upper gate electrode are electrically connected to each other.
However, in the same field of endeavor, Choi discloses the main silicon transistor (¶0074 discloses P-type transistor may be a polycrystalline transistor formed by using a semiconductor such as silicon as a semiconductor layer) further comprises: a sixth main transistor (T6) connected between a second main node (N3) connected to a first terminal of the first main transistor (D-TFT) and the light-emitting diode (OLED) (Fig. 4 and ¶0082 discloses sixth transistor T6 may be configured to switch an electrical connection between the third node N3 of the driving transistor D-TFT and a first electrode of the light emitting element ED), wherein at least one of the first main transistor, the second main transistor, the third main transistor, or the fourth main transistor (T7) has a structure in which the third lower gate electrode and the third upper gate electrode are electrically connected to each other (Fig. 4, ¶0071 and ¶0124-¶0126 discloses second lower gate electrode 308 of the second thin film transistor 360 may be electrically connected to the second upper gate electrode 314 of the second thin film transistor 360 to form a dual gate (or double gate)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang for the purpose of having lower off leakage at the OLED node.
Regarding claim 19, Zhang as modified doesn’t disclose the display apparatus of claim 18, wherein the pixel circuit further comprises: a first main capacitor connected between the first main node and the second main node; and a second main capacitor connected between the driving voltage line and the second main node.
However, in the same field of endeavor, Kim7812 discloses wherein the pixel circuit further comprises: a first main capacitor (Cst) connected between the first main node (gate of T1) and the second main node (second electrode of the hold capacitor); and a second main capacitor (Chold) connected between the driving voltage line (ELVDD) and the second main node (second electrode of the hold capacitor) (Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Zhang in order to maintain the voltage of the overlapping electrode (the second driving gate electrode) of the driving transistor T1 and the one electrode (the anode) of the light emitting diode LED constant (¶0067).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626
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