DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant states that this application is a continuation or divisional application of the prior-filed application. A continuation or divisional application cannot include new matter. Applicant is required to delete the benefit claim or change the relationship (continuation or divisional application) to continuation-in-part because this application contains the following matter not disclosed in the prior-filed application:
“In some embodiments, a method (of manufacturing an integrated circuit) includes: doping portions of a substrate resulting in active regions (ARs) that extend in a first direction, the ARs including alpha and beta ones of the ARs, the doping portions including: for a given length of the substrate in the first direction, differently doping the alpha and beta ARs correspondingly to have first and second heights relative to a perpendicular second direction, the second height being smaller than the first height such that areas of the beta ARs being smaller than areas of the alpha ARs for the given length; forming components of transistors (transistor components) in corresponding areas of corresponding ones of the alpha and beta ARs; depositing gate lines extending in the first direction and being over corresponding ones of the transistor components; removing portions of the gate lines resulting in corresponding gate segments; relative to the first direction, top and bottom boundaries of transistor regions being at least proximal correspondingly to ends of the one or more gate segments; gate lengths of corresponding first ones of the transistors in the alpha ARs being larger than gate lengths of corresponding second ones of the transistors in the beta ARs; forming metallization segments coupled to corresponding ones of the transistor components,” was not described in the prior-filed applications and is therefore new matter.
Claim Objections
Claims 2 and 11 are objected to because of the following informalities:
a) regarding claim 2:
In claim 2, lines 6-7 the limitation, “the first clocked inverter being comprised of corresponding ones of the second transistors,” is a duplicate of the limitation in lines 12-13 of claim 1.
b) regarding claim 11:
In claim 11, line 14 the Examiner suggests deleting “and second” before “and second inverters”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
a) regarding claim 15:
The limitations, “A method of manufacturing an integrated circuit, the method comprising: doping portions of a substrate resulting in active regions (ARs) that extend in a first direction, the ARs including alpha and beta ones of the ARs, the doping portions including: for a given length of the substrate in the first direction, differently doping the alpha and beta ARs correspondingly to have first and second heights relative to a perpendicular second direction, the second height being smaller than the first height such that areas of the beta ARs being smaller than areas of the alpha ARs for the given length; forming components of transistors (transistor components) in corresponding areas of corresponding ones of the alpha and beta ARs; depositing gate lines extending in the first direction and being over corresponding ones of the transistor components; removing portions of the gate lines resulting in corresponding gate segments; relative to the first direction, top and bottom boundaries of transistor regions being at least proximal correspondingly to ends of the one or more gate segments; gate lengths of corresponding first ones of the transistors in the alpha ARs being larger than gate lengths of corresponding second ones of the transistors in the beta ARs; forming metallization segments coupled to corresponding ones of the transistor components,” fail to comply with the written description requirement. Other than merely reciting the claim limitations the specification provides no explanation for any of the steps claimed as part of the method of manufacturing an integrated circuit. For example, what is the process for “depositing gate lines” and “removing portions of the gate lines”? The application provides no explanation and therefore fails to comply with the written description requirement.
b) regarding claims 16-20:
The claims are rejected based on their dependence on claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (US Pub. No. 2020/0058681).
a) regarding claim 1:
Lai et al. discloses an integrated circuit (Figures 6A and 6B) comprising:
active regions including wide active regions (632) and narrow active regions (634) extending in a first direction;
transistors including components formed in the active regions (paragraph [0016]);
gate widths of corresponding first ones (HA) of the transistors in the wide active regions being larger than gate widths of corresponding second ones (HB) of the transistors in the narrow active regions (paragraph [0019]);
a first latch (P3) including a first inverter (618) and a first clocked inverter (620) coupled together in parallel;
the first inverter (618) being comprised of corresponding ones of the first transistors (HA); and
the first clocked inverter (620) being comprised of corresponding ones of the second transistors (HB).
b) regarding claim 2:
Lai et al. discloses the integrated circuit of claim 1, further comprising:
a second latch (P5) including a second inverter (626) and a second clocked inverter (628) coupled together in parallel;
the second inverter (626) being comprised of corresponding ones of the first transistors (HA); and
the first clocked inverter (620) being comprised of corresponding ones of the second transistors (HB); and
wherein:
the second inverter (626) is comprised of corresponding ones of the first transistors (HA);
the second clocked inverter (628) is comprised of corresponding ones of the second transistors (HB); and
the first latch (P3) and the second latch (P5) are arranged correspondingly as a master latch and as slave latch representing a master-slave latch arrangement (paragraph [0028]).
c) regarding claim 3:
Lai et al. discloses the integrated circuit of claim 2, further comprising:
a transmission gate (P4) coupled between the first latch (P3) and the second latch (P5); and
wherein:
the transmission gate (P4) is comprised of corresponding ones of the first transistors (HA).
d) regarding claim 4:
Lai et al. discloses the integrated circuit of claim 2, further comprising:
an output driver (P6) coupled to an output of the second latch (P5); and
wherein:
the output driver (P6) is comprised of corresponding ones of the first transistors (HA).
e) regarding claim 5:
Lai et al. disclose the integrated circuit of claim 2, further comprising:
a multiplexer (P1) coupled to an input of the first latch (P3); and
wherein:
the multiplexer (P1) is comprised of corresponding ones of the first transistors (HA).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,003,242 (hereinafter ‘242 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are a broader recitation of the ‘242 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use the teachings of claims 1-18 of the '242 patent as general teachings of a latch as claimed in the present application. The instant claims obviously encompass the claimed invention in the '242 patent and differ only in terminology.
Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,388,428 (hereinafter ‘428 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are a broader recitation of the ‘428 patent. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use the teachings of claims 1-18 of the '428 patent as general teachings of a latch as claimed in the present application. The instant claims obviously encompass the claimed invention in the '428 patent and differ only in terminology.
Conclusion
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/PATRICK O NEILL/Primary Examiner, Art Unit 2836
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