DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Notes:
The limitation of the gate electrode of T1 being connected to the sixth node is hereby read as being broader than, and therefore taught by the more specific limitation of the “diode-connected” transistor of claim 1 of Patent No. US: 12,347,391. This is elaborated in the comparison table in the forthcoming action, also please refer to T1 in figure 6 in the instant application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No. US: 12,347,391 in view of Weng (Publication number: US 2021/0366353).
Although the claims at issue are not identical, they are not patentably distinct from each other because:
Consider Claim 1, the limitations of claim 1 are taught by the limitations of claim 1 of U.S. Patent No. US: 12,347,391 as shown by the comparison table below.
However, claim 1 of U.S. Patent No. US: 12,347,391 (hereinafter In et al), does not specifically show an output signal of a previous stage or a start pulse.
In related art, Weng (Publication number: US 2021/0366353) shows an output signal of a previous stage or a start pulse (see figures 8A-8B; and paragraphs 111-113).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Weng into the teaching of In et al in order to stabilize levels of the output signals (see Weng; paragraphs 3-5).
Claim 19 is similar in scope to claim 1, therefore claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over the same reasons discussed in regards to claim 1.
Claim 2 is taught by limitations in claim 23 of In et al.
Claim 3 is taught by limitations in claim 1 of In et al.
Claim 4 is taught by limitations in claim 15 of In et al.
Claim 5 is taught by limitations in claim 1 of In et al.
Claim 6 is taught by limitations in claim 1 of In et al.
Claim 7 is taught by limitations in claim 17 of In et al.
Consider Claim 8, In et al in view of Weng do not specifically show that each of the first power and the second power is a DC voltage. However, the USPTO takes official notice that it is well known and expected in the art that each of the first power and the second power is a DC voltage improve lifespan of the drivers.
Claim 9 is taught by limitations in claim 18 of In et al.
Claim 10 is taught by limitations in claim 15 of In et al.
Claim 11 is taught by limitations in claim 15 of In et al.
Claim 12 is taught by limitations in claim 7 of In et al.
Claim 13 is taught by limitations in claim 11 of In et al.
Claim 14 is taught by limitations in claim 12 of In et al.
Claim 15 is taught by limitations in claim 12 of In et al.
Claim 16 is taught by limitations in claim 12 of In et al.
Claim 17 is taught by limitations in claim 8 of In et al.
Claim 18 is taught by limitations in claim 9 of In et al.
Claim 20 is taught by limitations in claim 21 of In et al.
19/256,059) Instant Application
Patent No. US: 12,347,391
1. A gate driver comprising a stage, the stage comprising: a first terminal configured to receive an output signal of a previous stage or a start pulse; a second terminal configured to receive a first signal; a third terminal configured to receive a second signal; a first power line configured to receive a first power; a second power line configured to receive a second power; a first part comprising a fourth transistor, wherein the fourth transistor is connected between the first terminal and a first node and comprises a gate electrode connected to the second terminal; a second part comprising a seventh transistor and an eighth transistor, wherein the seventh transistor is connected between the first power line and an output terminal and comprises a gate electrode connected to a third node, and wherein the eighth transistor is connected between the second power line and the output terminal and comprises a gate electrode connected to a fourth node; a third part comprising an eleventh transistor, wherein the eleventh transistor is connected between the second power line and the fourth node and comprises a gate electrode connected to the first node; and a fourth part comprising a first transistor, wherein the first transistor is connected between the third node and a sixth node and comprises a gate electrode electrically connected to the sixth node.
1. A stage comprising: a first input terminal; a second input terminal configured to receive a first clock signal; a third input terminal configured to receive a second clock signal; an output terminal configured to output a gate signal; an input part comprising a fourth transistor connected between the first input terminal and a first node, and comprising a gate electrode electrically connected to the second input terminal; an output part comprising: a seventh transistor connected between a first power line and the output terminal, and comprising a gate electrode electrically connected to a third node; and an eighth transistor connected between a second power line and the output terminal, and comprising a gate electrode electrically connected to a fourth node; a first signal-processing part comprising an eleventh transistor connected between the second power line and the fourth node, and comprising a gate electrode electrically connected to the first node; and a second signal-processing part comprising a first transistor diode-connected between the third node and a sixth node, and comprising a gate electrode electrically connected to the sixth node.
Allowable Subject Matter
Claims 1-20 are allowed.
The following is an examiner's statement of reasons for allowance: The best prior art of
record, i.e., Weng (Publication number: US 2021/0366353) in view of Yang et al (Publication
number: US 2021/0217350) in view of Hong (Publication number: US 2020/0160805) do not
specifically show the limitations of " wherein the fourth transistor is connected between the first terminal and a first node and comprises a gate electrode connected to the second terminal; a second part comprising a seventh transistor and an eighth transistor, wherein the seventh transistor is connected between the first power line and an output terminal and comprises a gate electrode connected to a third node, and wherein the eighth transistor is connected between the second power line and the output terminal and comprises a gate electrode connected to a fourth node; a third part comprising an eleventh transistor, wherein the eleventh transistor is connected between the second power line and the fourth node and comprises a gate electrode connected to the first node; and a fourth part comprising a first transistor, wherein the first transistor is connected between the third node and a sixth node and comprises a gate electrode electrically connected to the sixth node.”
Conclusion
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 03/17/2026