DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to a chain of prior applications, the earliest of which is U.S. Application 15/204,243 (now US Patent 10,678,545), filed July 7, 2016.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statements dated July 1, 2025 and May 20, 2026 is acknowledged by the Examiner and the cited references have been considered, except as otherwise indicated, in the examination of the claims now pending. Copies of the PTOL-1449s initialed and dated by the Examiner are attached to the instant office action. The foreign office action was stricken through because the Applicant failed to comply with 37 CFR 1.98(3), which requires, “(i) A concise explanation of the relevance, as it is presently understood by the individual designated in § 1.56(c) most knowledgeable about the content of the information, of each patent, publication, or other information listed that is not in the English language. The concise explanation may be either separate from applicant’s specification or incorporated therein. (ii) A copy of the translation if a written English-language translation of a non-English-language document, or portion thereof, is within the possession, custody, or control of, or is readily available to any individual designated in § 1.56(c).”
Drawings
The drawings are objected to because of the following informalities.
Figure 30 includes text, i.e., 2718 and 2728, that lacks underlining and lead lines. One or the other is required. The figure therefore fails to comply with 37 CFR 1.84(q), which states, “Lead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed. Such a reference character must be underlined to make it clear that a lead line has not been left out by mistake.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim2 is objected to because of the following informalities.
Claim 2 recites, “a third instruction that proceeds the second instruction.” This appears to be a typographical error. Applicant may have intended “a third instruction that precedes the second instruction.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,346,698. Although the claims at issue are not identical, they are not patentably distinct from each other because they are obvious variants. For example, claim 1 of ‘698 patent does not recite a register file. However, as discussed below, this limitation is disclosed by Anderson, e.g., at Figure 5. The bold language below in claim 1 of the 698 patent corresponds to the elements in claim 1 of the instant application.
Claim 1 under examination in 19/256,267
Claim 1 in 12,346,698
Claim 1: (19/256,267) A device comprising:
a processor functional unit;
a register file coupled to the processor functional unit and that includes a first register;
a cache controller coupled to the processor functional unit and that includes a second register; and
an instruction decoder coupled to the processor functional unit and capable of:
in response to a first coding of an instruction source field that specifies the first register, cause the processor functional unit to retrieve a first set of data from the first register;
in response to a second coding of the instruction source field that specifies the second register, cause the processor functional unit to retrieve a second set of data from the second register without replacing the second set of data in the second register; and
in response to a third coding of the instruction source field that specifies the second register:
cause the processor functional unit to retrieve a third set of data from the second register; and
cause the cache controller to replace the third set of data in the second register with a fourth set of data; and
in response to a packet of instructions that includes a first instruction having the second coding and a second instruction having the third coding, cause contents of the second register to be replaced.
Claim 1: (12,346,698) A device comprising:
a cache control circuit that includes:
a cache interface configured to couple to a cache memory and to retrieve a set of data elements from the cache memory that includes a first data element and a second data element; and
a head register configured to store the first data element; and
an instruction decoder coupled to the cache control circuit and configured to:
receive an instruction packet that includes a set of instructions to be executed in parallel that includes:
a first instruction that specifies to read the first data element from the head register and to store the second data element in the head register; and
a second instruction that specifies to read the first data element from the head register, wherein the second instruction does not specify to store the second data element in the head register; and
based on the instruction packet, cause the cache control circuit to store the second data element in the head register.
The remaining independent claims include similar features and are likewise rejected. The dependent claims are rejected over corresponding dependent claims of the reference application. Tables comparing these claims to the corresponding claims of the reference are omitted in the interest of brevity.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,693,660. Although the claims at issue are not identical, they are not patentably distinct from each other because they are obvious variants. For example, claim 1 of ‘660 patent does not recite a register file. However, as discussed below, this limitation is disclosed by Anderson, e.g., at Figure 5. The bold language below in claim 1 of the ’660 patent corresponds to the elements in claim 1 of the instant application.
Claim 1 under examination in 19/256,267
Claim 1 in 11,693,660
Claim 1: (19/256,267) A device comprising:
a processor functional unit;
a register file coupled to the processor functional unit and that includes a first register;
a cache controller coupled to the processor functional unit and that includes a second register; and
an instruction decoder coupled to the processor functional unit and capable of:
in response to a first coding of an instruction source field that specifies the first register, cause the processor functional unit to retrieve a first set of data from the first register;
in response to a second coding of the instruction source field that specifies the second register, cause the processor functional unit to retrieve a second set of data from the second register without replacing the second set of data in the second register; and
in response to a third coding of the instruction source field that specifies the second register:
cause the processor functional unit to retrieve a third set of data from the second register; and
cause the cache controller to replace the third set of data in the second register with a fourth set of data; and
in response to a packet of instructions that includes a first instruction having the second coding and a second instruction having the third coding, cause contents of the second register to be replaced.
Claim 1: (11,693,660) A processor comprising:
a plurality of functional units;
a streaming engine that includes a stream head register configured to store a portion of a data stream; and
an instruction decoder coupled to the instruction decoder and the streaming engine, wherein the instruction decoder is configured to:
receive an instruction execute packet that includes a first instruction and a second instruction, wherein:
the first instruction includes a first source operand that specifies the stream head register and whether to advance the data stream; and
the second instruction includes a second source operand that specifies the stream head register and whether to advance the data stream;
in response to the first instruction, provide a first value of the data stream stored in the stream head register to a first functional unit of the plurality of functional units; and
in response to the second instruction: provide the first value stored in the stream head register to a second functional unit of the plurality of functional units; and
replace the first value in the stream head register with a second value of the data stream.
The remaining independent claims include similar features and are likewise rejected. The dependent claims are rejected over corresponding dependent claims of the reference application. Tables comparing these claims to the corresponding claims of the reference are omitted in the interest of brevity.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 47 of U.S. Patent No. 10,678,545. Although the claims at issue are not identical, they are not patentably distinct from each other because they are obvious variants. The bold language below in claim 47 of the ‘545 patent corresponds to the elements in claim 1 of the instant application.
Claim 1 under examination in 19/256,267
Claim 47 in 10,678,545
Claim 1: (19/256,267) A device comprising:
a processor functional unit;
a register file coupled to the processor functional unit and that includes a first register;
a cache controller coupled to the processor functional unit and that includes a second register; and
an instruction decoder coupled to the processor functional unit and capable of:
in response to a first coding of an instruction source field that specifies the first register, cause the processor functional unit to retrieve a first set of data from the first register;
in response to a second coding of the instruction source field that specifies the second register, cause the processor functional unit to retrieve a second set of data from the second register without replacing the second set of data in the second register; and
in response to a third coding of the instruction source field that specifies the second register:
cause the processor functional unit to retrieve a third set of data from the second register; and
cause the cache controller to replace the third set of data in the second register with a fourth set of data; and
in response to a packet of instructions that includes a first instruction having the second coding and a second instruction having the third coding, cause contents of the second register to be replaced.
Claim 47: (10,678,545) A data processing device comprising:
an instruction decoder to decode instructions recalled from an instruction memory by determining, wherein each instruction includes a first field having a first plurality of bits and a second field having a second plurality of bits, wherein the first plurality of bits indicates one of a plurality of available bit codings;
a plurality of functional units, each functional unit configured to perform a data processing operation in response to an operand specified by an instruction;
a first data register file that includes a first set of data registers, the first data register file being a global data register file that is configured to be accessible by each one of the plurality of functional units;
a second data register file that includes a second set of data registers, the second data register file being a local data register file that is configured to be accessible by only some of the plurality of functional units; and
a streaming engine to recall a data stream from a memory in response to a stream start instruction, wherein the data stream includes a sequence of data elements, and wherein the streaming engine includes a stream head register to store a data element of the data stream that is immediately available to the plurality of functional units;
wherein, upon receiving an instruction execute packet that includes at least a first instruction and a second instruction, the instruction decoder is configured to decode the first and second instructions to:
determine a first source operand based on the first plurality of bits contained in the first field of the first instruction;
determine a first opcode based on the second plurality of bits contained in the second field of the first instruction, wherein the first opcode identifies one of the plurality of functional units as a first target functional unit and identifies a first data processing operation to be performed by the first target functional unit;
determine a second source operand based on the first plurality of bits contained in the first field of the second instruction;
determine a second opcode based on the second plurality of bits contained in the second field of the second instruction, wherein the second opcode identifies another one of the plurality of functional units as a second target functional unit and identifies a second data processing operation to be performed by the second target functional unit; and
wherein, for each of the first and second instructions:
when the first plurality of bits has a bit coding belonging to a first subset of the available bit codings, the first plurality of bits identifies a data register of the global data register file that contains a respective one of the first source operand and the second source operand, and the respective one of the first source operand and the second source operand contained in the identified data register of the global data register file is supplied to a source operand input of a respective one of the first target functional unit and the second tarqet functional unit;
when the first plurality of bits has a bit coding belonging to a second subset of the available bit codings, the first plurality of bits identifies a data register of the local data register file that contains the respective one of the first source operand and the second source operand, and the respective one of the first source operand and the second source operand contained in the identified data register of the local data register file is supplied to the source operand input of the respective one of the first target functional unit and the second tarqet functional unit;
when the first plurality of bits has a first predetermined bit coding of the available bit codings, the first plurality of bits identifies the stream head register of the streaming engine as containing the respective one of the first source operand and the second source operand, and the respective one of the first source operand and the second source operand contained in the stream head register is supplied to the source operand input of the respective one of the first target functional unit and the second target functional unit; and
when the first plurality of bits has a second predetermined bit coding of the available bit codings, the first plurality of bits identifies the stream head register of the streaming engine as containing the respective one of the first source operand and the second source operand, and the respective one of the first source operand and the second source operand contained in the stream head register is supplied to the source operand input of a respective one of the first target functional unit and the second tarqet functional unit, and the streaming engine causes a next data element of the sequence of data elements to be stored in the stream head register; and
wherein, when the first plurality of bits of the first instruction has the first predetermined bit coding and when the first plurality of bits of the second instruction has the second predetermined bit coding, the streaming engine is responsive to the first and second instructions to cause a source operand contained in the stream head register to be supplied to each of the first and second target functional units and to cause the next data element of the sequence of data elements to be stored in the stream head register in response to the first plurality of bits of the second instruction having the second predetermined bit coding and irrespective of the first plurality of bits of the first instruction having the first predetermined bit coding.
The remaining independent claims include similar features and are likewise rejected. The dependent claims are rejected over corresponding dependent claims of the reference application. Tables comparing these claims to the corresponding claims of the reference are omitted in the interest of brevity.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 9,606,803. Although the claims at issue are not identical, they are not patentably distinct from each other because they are obvious variants. The bold language below in claims 1 and 2 of the ‘803 patent corresponds to the elements in claim 1 of the instant application.
Claim 1 under examination in 19/256,267
Claims in 9,606,803
Claim 1: (19/256,267) A device comprising:
a processor functional unit;
a register file coupled to the processor functional unit and that includes a first register;
a cache controller coupled to the processor functional unit and that includes a second register; and
an instruction decoder coupled to the processor functional unit and capable of:
in response to a first coding of an instruction source field that specifies the first register, cause the processor functional unit to retrieve a first set of data from the first register;
in response to a second coding of the instruction source field that specifies the second register, cause the processor functional unit to retrieve a second set of data from the second register without replacing the second set of data in the second register; and
in response to a third coding of the instruction source field that specifies the second register:
cause the processor functional unit to retrieve a third set of data from the second register; and
cause the cache controller to replace the third set of data in the second register with a fourth set of data; and
in response to a packet of instructions that includes a first instruction having the second coding and a second instruction having the third coding, cause contents of the second register to be replaced.
Claim 1: (9,606,803) A digital signal processor comprising:
a data register file including a plurality of data registers designed by register number storing data;
an instruction memory storing instructions each specifying a data processing operation and at least one data operand by register number;
an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand, said instructions including a stream start instruction and a stream operand instruction;
at least one operational unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register;
a stream engine connected to said instruction decoder operable in response to a stream start instruction to recall from an external memory a stream of an instruction specified plurality of data elements;
a stream head register distinct from said plurality of data registers of said data register file, connected to said stream engine and readable by said at least one operational unit as an operand, said stream head register sequentially storing a next recalled data element of said stream of the instruction specified plurality of data elements for use as an operand; and
wherein said at least one operational unit is responsive to a stream operand instruction to perform a specified data processing operation determined by the instruction decoder and to receive at least one operand from said stream head register.
Claim 2. The digital signal processor of claim 1,wherein:
said stream operand instruction includes a stream operand read only instruction and a stream operand read and increment instruction;
said at least one operational unit receiving as an operand data stored in said stream head register in response to a stream operand read only instruction and a stream operand read and increment instruction; and
said stream engine storing a next fetched data element in said stream head register in response to a stream operand read and increment instruction.
The remaining independent claims include similar features and are likewise rejected. The dependent claims are rejected over corresponding dependent claims of the reference application. Tables comparing these claims to the corresponding claims of the reference are omitted in the interest of brevity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2015/0019840 by Anderson et al. (previously cited and hereinafter referred to as “Anderson”).
Regarding claim 1, Anderson discloses:
a device comprising: a processor functional unit (Anderson discloses, at ¶ [0053], a processor that includes functional units.);
a register file coupled to the processor functional unit and that includes a first register (Anderson discloses, at ¶ [0054], register files.);
a cache controller coupled to the processor functional unit and that includes a second register (Anderson discloses, at ¶ [0050], a streaming engine that controls cache and provides data to a functional unit. As disclosed at Figure 22 and related description, the streaming engine includes registers, e.g., holding registers.); and
an instruction decoder coupled to the processor functional unit and capable of (Anderson discloses, at ¶ [0073], decoding.):
in response to a first coding of an instruction source field that specifies the first register, cause the processor functional unit to retrieve a first set of data from the first register (Anderson discloses, at ¶ [0073], instructions that specify source registers, which discloses retrieving data from the first register.);
in response to a second coding of the instruction source field that specifies the second register, cause the processor functional unit to retrieve a second set of data from the second register without replacing the second set of data in the second register (Anderson discloses, at ¶ [0164], instructions that read data from the head register, which discloses a second coding of the instruction source field.); and
in response to a third coding of the instruction source field that specifies the second register: cause the processor functional unit to retrieve a third set of data from the second register; and cause the cache controller to replace the third set of data in the second register with a fourth set of data (Anderson discloses, at ¶ [0164], instructions that read data from the head register and advance, which discloses a third coding of the instruction source field.)….
Anderson does not explicitly disclose in response to a packet of instructions that includes a first instruction having the second coding and a second instruction having the third coding, cause contents of the second register to be replaced.
However, Anderson discloses packets of instructions that can be executed in parallel or sequentially. See, e.g., ¶ [0086]. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include the read and read/advance instructions in a packet in order to perform desired operations, e.g., reading data one or more times. It would also have been obvious to execute the read instruction prior to the read/advance instruction in order to perform desired operations, e.g., reading data one or more times. Doing so would result in replacement of the contents of the second register.
Regarding claim 2, Anderson, as modified, discloses the elements of claim 1, as discussed above. Anderson also discloses:
the instruction decoder is capable of, in response to a third instruction that proceeds the second instruction, cause the cache controller to retrieve a fifth set of data from a cache memory (Anderson discloses, at ¶ [0092], prefetching data.).
Anderson does not explicitly disclose the fifth set of data includes the third set of data and the fourth set of data. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to prefetch the third and fourth sets of data in order to increase processing speed by reducing memory access delays.
Regarding claim 4, Anderson, as modified, discloses the elements of claim 1, as discussed above. Anderson also discloses:
a set of processor functional units that includes the processor functional unit, wherein the register file is global with respect to the set of processor functional units (Anderson discloses, at ¶ [0053], CPUs that include multiple execution units. Anderson also discloses, at Figure 5 and related description, a global register file.).
Regarding claim 5, Anderson, as modified, discloses the elements of claim 1, as discussed above. Anderson also discloses:
a set of processor functional units that includes the processor functional unit, wherein the register file is local with respect to the processor functional unit (Anderson discloses, at ¶ [0053], CPUs that include multiple execution units. Anderson also discloses, at Figure 5 and related description, a local register file.).
Regarding claim 6, Anderson, as modified, discloses the elements of claim 1, as discussed above. Anderson also discloses:
the cache controller includes a third register (Anderson discloses at Figure 22 and related description, the streaming engine includes registers, e.g., holding registers.); and
the instruction decoder is capable of: in response to a fourth coding of the instruction source field that specifies the third register, cause the processor functional unit to retrieve a fifth set of data from the third register without replacing the fifth set of data in the third register (Anderson discloses, at ¶ [0164], instructions that read data from the head register, which discloses a second coding of the instruction source field.); and
in response to a fifth coding of the instruction source field that specifies the third register: cause the processor functional unit to retrieve a sixth set of data from the third register; and cause the cache controller to replace the sixth set of data in the third register with a seventh set of data (Anderson discloses, at ¶ [0164], instructions that read data from the head register and advance, which discloses a third coding of the instruction source field.).
Regarding claim 7, Anderson, as modified, discloses the elements of claim 6, as discussed above. Anderson also discloses:
the cache controller includes: a memory interface (Anderson discloses, at Figure 22 and related description, L2 interfaces.);
a first address generator coupled to the memory interface and capable of: causing the memory interface to receive a first data stream; and causing the second register to store a subset of the first data stream (Anderson discloses, at Figure 22 and related description, address generators that generate the addresses used to retrieve and store the data streams.); and
a second address generator coupled to the memory interface and capable of: causing the memory interface to receive a second data stream; and causing the third register to store a subset of the second data stream (Anderson discloses, at Figure 22 and related description, address generators that generate the addresses used to retrieve and store the data streams.).
Regarding claim 8, Anderson, as modified, discloses the elements of claim 1, as discussed above. Anderson also discloses:
a level-two (L2) cache memory, wherein the cache controller is an L2 cache memory controller (Anderson discloses, at Figure 4 and related description, L2 memory. As disclosed at Figure 22 and related description, the streaming engine includes L2 interfaces, which discloses being an L2 cache memory controller.).
Regarding claim 9, Anderson discloses:
a method comprising: receiving a first instruction that includes an instruction source field, wherein the instruction source field of the first instruction specifies a first register of a register file (Anderson discloses, at ¶ [0073], instructions that specify source registers, which discloses retrieving data from the first register.);
based on the first instruction, providing a first set of data from the first register to a processing circuit (Anderson discloses, at ¶ [0073], instructions that specify source registers, which discloses retrieving data from the first register.);
receiving a packet…a second instruction and a third instruction that each include the instruction source field, wherein (Anderson discloses, at ¶ [0086], packets of instructions that can be executed in parallel or sequentially.):
the instruction source field of the second instruction specifies a second register of a cache controller and does not specify to replace contents of the second register (Anderson discloses, at ¶ [0164], instructions that read data from the head register, which discloses a second coding of the instruction source field.); and
the instruction source field of the third instruction specifies the second register of the cache controller and specifies to replace contents of the second register (Anderson discloses, at ¶ [0164], instructions that read data from the head register and advance, which discloses a third coding of the instruction source field.) ….
Anderson does not explicitly disclose that the aforementioned packet includes the aforementioned second and third instructions and based on the packet: providing a second set of data from the second register to the processing circuit; and replacing contents of the second register.
However, given Anderson’s disclosure of packets, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include the read and read/advance instructions in a packet in order to perform desired operations, e.g., reading data one or more times. It would also have been obvious to execute the read instruction prior to the read/advance instruction in order to perform desired operations, e.g., reading data one or more times. Doing so would result in replacement of the contents of the second register.
Regarding claim 10, Anderson, as modified, discloses the elements of claim 9, as discussed above. Anderson also discloses:
receiving a fourth instruction prior to the receiving of the packet; and based on the fourth instruction, causing the cache controller to retrieve the second set of data and store the second set of data in the second register (Anderson discloses, at ¶ [0092], prefetching.).
Regarding claim 12, Anderson, as modified, discloses the elements of claim 9, as discussed above. Anderson also discloses:
the processing circuit includes a set of functional units; and the register file is global with respect to the set of functional units (Anderson discloses, at ¶ [0053], CPUs that include multiple execution units. Anderson also discloses, at Figure 5 and related description, a global register file.).
Regarding claim 13, Anderson, as modified, discloses the elements of claim 9, as discussed above. Anderson also discloses:
the processing circuit includes a set of functional units that includes a first functional unit; and the register file is local with respect to the first functional unit (Anderson discloses, at ¶ [0053], CPUs that include multiple execution units. Anderson also discloses, at Figure 5 and related description, a local register file.).
Regarding claim 14, Anderson, as modified, discloses the elements of claim 9, as discussed above. Anderson also discloses:
receiving a fourth instruction that includes the instruction source field, wherein the instruction source field of the fourth instruction specifies a third register of the cache controller and specifies whether to replace contents of the third register (Anderson discloses, at ¶ [0164], instructions that read data from the head register, or read and advance, which discloses receiving a fourth instruction as claimed.); and
based on the fourth instruction, providing a third set of data from the third register to the processing circuit (Anderson discloses, at ¶ [0164], instructions that read data from the head register, or read and advance, which discloses providing data from the third register.).
Regarding claim 15, Anderson, as modified, discloses the elements of claim 9, as discussed above. Anderson also discloses:
the cache controller is a level-two (L2) cache controller (Anderson discloses, at Figure 4 and related description, L2 memory. As disclosed at Figure 22 and related description, the streaming engine includes L2 interfaces, which discloses being an L2 cache memory controller.).
Claims 3, 11, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of US Publication No. 2014/0115224 by Sanghai et al. (hereinafter referred to as “Sanghai”).
Regarding claim 3, Anderson, as modified, discloses the elements of claim 1, as discussed above. Anderson also discloses:
the processor functional unit is a first processor functional unit (Anderson discloses, at ¶ [0053], CPUs that include multiple execution units.);
the device further comprises a second processor functional unit coupled to the cache controller (Anderson discloses, at ¶ [0053], CPUs that include multiple execution units. As disclosed at ¶ [0050], the CPUs are connected to the streaming engines.);
the first instruction is associated with the first processor functional unit (Anderson discloses, at ¶ [0164], instructions to read the head register. Providing the read data to the appropriate functional unit is implicit.);
the second instruction is associated with the second processor functional unit (Anderson discloses, at ¶ [0164], instructions to read the head register. Providing the read data to the appropriate functional unit is implicit.); and
Anderson does not explicitly disclose the instruction decoder is capable of, in response to the packet of instructions that includes the first instruction and the second instruction, cause the contents of the second register to be provided to the first processor functional unit and to the second processor functional unit prior to the contents of the second register being replaced.
However, Anderson discloses packets of instructions that can be executed in parallel or sequentially. See, e.g., ¶ [0086]. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include the read and read/advance instructions in a packet in order to perform desired operations, e.g., reading data one or more times. It would also have been obvious to provide the desired data in the desired order in order to perform desired operations, e.g., reading data one or more times and ensuring correct operation.
Also in the same field of endeavor (e.g., processors) Sanghai discloses:
providing data to a first and second processing element (Sanghai discloses, at ¶ [0037, broadcasting an operand to multiple processing elements, i.e., functional units.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Anderson to include broadcasting to multiple functional units, as disclosed by Sanghai in order to improve performance by increasing parallelism and reducing associated memory access delays.
Regarding claim 11, Anderson, as modified, discloses the elements of claim 9, as discussed above. Anderson also discloses:
the providing of the second set of data includes: providing a first copy of the second set of data to a first functional unit of the processing circuit that is associated with the second instruction…(Anderson discloses, at ¶ [0164], a read instruction, which provides data to a functional unit associated with an instruction.).
Anderson does not explicitly disclose providing a second copy of the second set of data to a second functional unit of the processing circuit that is associated with the third instruction.
However, in the same field of endeavor (e.g., processors) Sanghai discloses:
providing data to a first and second processing element (Sanghai discloses, at ¶ [0037, broadcasting an operand to multiple processing elements, i.e., functional units.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Anderson to include broadcasting to multiple functional units, as disclosed by Sanghai in order to improve performance by increasing parallelism and reducing associated memory access delays.
Regarding claim 16, Anderson discloses:
…a first instruction that includes an instruction source field that specifies a first register of a register file, wherein the first instruction is configured to cause a first set of data to be provided by the first register (Anderson discloses, at ¶ [0073], instructions that specify source registers, which discloses retrieving data from the first register.); and
a packet that includes a second instruction and a third instruction that each include the instruction source field, wherein (Anderson discloses, at ¶ [0086], packets including instructions.):
the instruction source field of the second instruction specifies a second register of a cache controller and does not specify to replace contents of the second register (Anderson discloses, at ¶ [0164], instructions that read data from a head register of a streaming engine.);
the second instruction is configured to cause a second set of data to be provided by the second register (Anderson discloses, at ¶ [0164], instructions that read data from a head register of a streaming engine.);
the instruction source field of the third instruction specifies the second register of the cache controller and specifies to replace contents of the second register (Anderson discloses, at ¶ [0164], instructions that read and advance data from a head register of a streaming engine.);
the third instruction is configured to cause the second set of data to be provided by the second register (Anderson discloses, at ¶ [0164], instructions that read and advance data from a head register of a streaming engine.); and
the packet is configured to cause the contents of the second register to be replaced (Anderson discloses, at ¶ [0164], instructions that read and advance data from a head register of a streaming engine, which discloses replacing in the case of the read and advance instruction.).
Anderson does not explicitly disclose a non-transitory computer-readable medium comprising machine-executable instructions that include.
However, in the same field of endeavor (e.g., processors) Sanghai discloses:
non-transitory storage medium (Sanghai discloses, at ¶ [0047], non-transitory storage medium.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Anderson to include a storage media implementation, as disclosed by Sanghai, in order to facilitate production and distribution of the invention.
Regarding claim 17, Anderson, as modified, discloses the elements of claim 16, as discussed above. Anderson also discloses:
the instructions include a fourth instruction that precedes the packet and is configured to cause the second set of data to be stored in the second register (Anderson discloses, at ¶ [0092], prefetching data.).
Regarding claim 18, Anderson, as modified, discloses the elements of claim 16, as discussed above. Anderson also discloses:
the second instruction is configured to cause the second set of data to be provided by the second register to a first functional unit of a processor Anderson discloses, at ¶ [0164], a read instruction, which provides data to a functional unit associated with an instruction.); and
the third instruction is configured to cause the second set of data to be provided by the second register to a second functional unit of a processor Anderson discloses, at ¶ [0164], a read instruction, which provides data to a functional unit associated with an instruction.).
Regarding claim 19, Anderson, as modified, discloses the elements of claim 16, as discussed above. Anderson also discloses:
each of the second instruction and the third instruction specify the second register from among a set of registers of the cache controller Anderson discloses, at ¶ [0164], a read instruction, which provides data to a functional unit associated with an instruction.).
Regarding claim 20, Anderson, as modified, discloses the elements of claim 16, as discussed above. Anderson also discloses:
the cache controller is a level-two (L2) cache controller (Anderson discloses, at Figure 4 and related description, L2 memory. As disclosed at Figure 22 and related description, the streaming engine includes L2 interfaces, which discloses being an L2 cache memory controller.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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