DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
01/21/2026.This office action is in response to communication filed 01/21/2026. Claims 1, 5-6, 11, 14-15, and 18 have been amended, no claims have been canceled or added.
INFORMATION CONCERNING Specification:
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
One or more claims recite “bypassing”; the specification fails to provide proper antecedent basis for bypassing.
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
4. The independent claim 1, in part, recites the limitation:
“wherein the memory module is operable to concurrently provide one or more of the plurality of operating voltages to one or more first components of the plurality of components and to provide an additional voltage other than any of the plurality of operating voltages to one or more second components of the plurality of components, wherein the additional voltage is based on an input voltage received via one of the power connections, the input voltage being less than half the regulated voltage.”
The claimed specification does not appear to describe/support the above limitations as claimed. The independent claims 11 and 18 include similar limitations and are rejected based on the same ground of rejection. The dependent claims 2-10, 12-17 and 19 are rejected at least by virtue of their dependency from their respected independent claims.
5. Claims 2, 4, 11-17, and 19 recite, in part, the limitation:
“the circuitry bypassing the plurality of buck converters.” The claimed specification does not appear to describe/support the above limitation as claimed. Claim 4 is rejected based on its dependency from claim 2. The dependent claims 12-17 are rejected based on their dependency from independent claim 11.
6. Claims 3, 13, and 20 recite the limitations:
“wherein the regulated voltage is about 5V, and each of the plurality of operating voltages is less than 5V.”
The claimed specification does not appear to describe/support the above limitation as claimed.
Response to Remarks
7. Applicant’s Remarks have been fully considered and they are partly persuasive. In light of amendment of claims to change mother board of computer to host system and discreet to discrete, applicant arguments regarding these terms are persuadable. However, arguments regarding “the circuitry bypassing the plurality of buck converters” is not persuasible.
The arguments on pages 8-9 of the Remarks, under idem 2 “Bypassing and Additional voltage” heading, make a reference to para. [00145] of instant specification and recites that “the power module 1100 can be configured to be operated in at least three states in certain environments”. Then, Remarks make a reference to para. [00150] of the specification and states two voltages outputted from the power module 1100. One is output voltage 1102 provided through wire 108 and the second is voltage 1104, which is output of the buck converter 1124. The buck converter 1124 input is voltage1110, which is generated by the power element 1130 (e.g., circuitry or a portion of circuitry in addition to the buck converters, see Fig. 16). The power element 1130 is connect to and is taking its input directly from wire 1108, which provide voltage 1110 to the buck converters. Then page 9 of the Remarks recite:
“it can be seen from FIG. 16 that this additional voltage (voltage 1102) is provided to any of the DRAMS, FLASH, and FPGA (i.e., controller 1062) from the input power supply 1106 via circuitry including, e.g., wire 1108, which bypasses voltage conversion element 1120, as shown in FIG. 16 and as recited in claim 2.” (Emphasis added).
There are number of issues with the arguments:
The Remarks recites the wire 1108 (e.g., input voltage) bypasses voltage conversion element 1120 (e.g., buck converters) while the claims recites the circuitry bypasses buck converters (e.g., applicant argues subject matter that is not in the claims).
The wire 108 is not connect to the buck converter and never passes through the buck converters.
The circuitry, not defined in specification or the Remarks, examiner assume that the power circuitry comprises power elements 1130 and 1140 (e.g., combination of 1144, 1146, and 1142 in the power module shown in Fig. 16), which provide input or feed the buck converters.
The wire 1108 could have been bypassed elements 1144 and 1130 but these elements use the voltage supplied on wire 108.
One good example of bypassing, might be “bypass cache”. For example cache is high speed buffer placed between a processor (e.g., host) and main memory to temporary store data before the passed or written to the main memory. It might be some reasons (advantages) to store or write some types of data directly to main memory (e.g., avoiding or bypassing cache).
Therefore, Applicant arguments regarding the “circuitry bypassing the plurality of buck converters” is not persuasive.
Regarding the rejection under 35 USC §102(a), first paragraph, page 9 of the Remarks disagrees with rejection of limitation:
“wherein the memory module is operable to concurrently provide one or more of the plurality of operating voltages to one or more first components of the plurality of components and to provide an additional voltage other than any of the plurality of operating voltages to one or more second components of the plurality of components, wherein the additional voltage is based on an input voltage received via one of the power connections, the input voltage being less than half the regulated voltage.”
Applicant on pages 9-12 of the Remarks make references to different portions of the specification and describes one or more voltages are provided to different components. The Examiner does not dispute that a plurality voltages provided, and even a given voltage provided to a plurality components. However, The specification does not describe/or support and applicant’s arguments are not persuasive that specification describes limitation(s): ”the memory module is operable to concurrently provide one or more of the plurality of operating voltages to one or more first components of the plurality of components and to provide an additional voltage other than any of the plurality of operating voltages to one or more second components of the plurality of components”, as recited in the claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see htto://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/HASHEM FARROKH/Primary Examiner, Art Unit 2138