DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 19/262117 filed on July 8, 2025 in which Claims 1-20 are presented for examination.
Status of Claims
Claims 1-20 are pending. Claims 1-20 are rejected under 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 10, 11, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) and further in view of Storm (US Patent Application 2024/0004752).
Claim 1, Yang teaches a memory module (View Yang ¶ 7; semiconductor memory system includes a processor and a stacked memory which are mounted over a substrate including a plurality of external connection terminals), comprising: a circuit substrate (View Yang ¶ 7; semiconductor memory system includes a processor and a stacked memory which are mounted over a substrate including a plurality of external connection terminals); at least one memory chip arranged on the circuit substrate (View Yang ¶ 5, 7; a memory and a processor may be integrated into one chip); a data collecting circuit arranged on the circuit substrate and electrically connected to the at least one memory chip (View Yang ¶ 19, 39; compression unit includes a plurality of XOR gates XOR1 to XOR4 (i.e., exclusive OR gates) and a plurality of registers REG1 to REG4. The plurality of XOR gates XOR1 to XOR4 are configured to receive the respective test patterns T0 to T3, and the plurality of registers REG1 to REG4 are alternately connected to the XOR gates XOR1 to XOR4, thereby forming a chain structure); and a connection interface arranged on the circuit substrate and electrically connected to the data collecting circuit (View Yang ¶ 7, 19, 39; semiconductor memory system includes a processor and a stacked memory which are mounted over a substrate including a plurality of external connection terminals).
Yang does not explicitly teach wherein for testing the memory module, the data collecting circuit is configured to receive a signal transmitted between a controller external to the memory module and the at least one memory chip, process the signal to generate a processed signal, and teach transmit the processed signal to a test monitor through the connection interface
However, Lin teaches wherein for testing the memory module, the data collecting circuit is configured to receive a signal transmitted between a controller external to the memory module and the at least one memory chip (View Lin ¶ 8; obtaining a pre-processed signal according to a received signal received by the receiving device, wherein the pre-processed signal comprises a mixture of a plurality of transmitted signals from the plurality of transmitting devices), process the signal to generate a processed signal (View Lin ¶ 8; the plurality of transmitted signals are generated according to a plurality of signatures and encoded according to a plurality of data signals).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yang with wherein for testing the memory module, the data collecting circuit is configured to receive a signal transmitted between a controller external to the memory module and the at least one memory chip, process the signal to generate a processed signal since it is known in the art that a signal can be processed (View Lin ¶ 8). Such modification would have allowed a processed signal to determine operational status.
Yang and Lin do not teach transmit the processed signal to a test monitor through the connection interface.
However, Storm teaches transmit the processed signal to a test monitor through the connection interface (View Storm ¶ 16; retrieve information, such as signal information, log information, state information, etc. stored by the components of the memory sub-system to analyze the signal information, log information, and/or state information to determine potential causes that led to the failures and/or fault conditions experienced by the components of the memory sub-system in order to triage the memory sub-system or the components thereof).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with transmit the processed signal to a test monitor through the connection interface since it is known in the art that a processed signal can be transmitted (View Storm ¶ 16). Such modification would have allowed a processed signal to be tested.
Claim 8, Yang teaches a method for testing a memory module (View Yang ¶ 5, 7, 8; a test circuit is inserted into the semiconductor memory system and a test result obtained by the test circuit is checked through a test pin of the substrate; a memory and a processor may be integrated into one chip), the memory module having at least one memory chip (View Yang ¶ 7, 8; a memory and a processor may be integrated into one chip), a data collecting circuit electrically connected to the at least one memory chip (View Yang ¶ 19, 39; compression unit includes a plurality of XOR gates XOR1 to XOR4 (i.e., exclusive OR gates) and a plurality of registers REG1 to REG4. The plurality of XOR gates XOR1 to XOR4 are configured to receive the respective test patterns T0 to T3, and the plurality of registers REG1 to REG4 are alternately connected to the XOR gates XOR1 to XOR4, thereby forming a chain structure), and a connection interface electrically connected to the data collecting circuit (View Yang ¶ 7, 19, 39; semiconductor memory system includes a processor and a stacked memory which are mounted over a substrate including a plurality of external connection terminals).
Yang does not explicitly teach the data collecting circuit configured to process a signal transmitted between a controller external to the memory module and the at least one memory chip to generate a processed signal, the method comprising: receiving, by a test monitor, the processed signal from the data collecting circuit via the connection interface; encoding, by the test monitor, the processed signal to generate log information; and determining, by the test monitor, an operation status of the memory module according to the log information.
However, Lin teaches the data collecting circuit configured to process a signal transmitted between a controller external to the memory module and the at least one memory chip to generate a processed signal (View Lin ¶ 8; obtaining a pre-processed signal according to a received signal received by the receiving device, wherein the pre-processed signal comprises a mixture of a plurality of transmitted signals from the plurality of transmitting devices), the method comprising: receiving, by a test monitor, the processed signal from the data collecting circuit via the connection interface (View Lin ¶ 8; the plurality of transmitted signals are generated according to a plurality of signatures and encoded according to a plurality of data signals).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Yang with the data collecting circuit configured to process a signal transmitted between a controller external to the memory module and the at least one memory chip to generate a processed signal, the method comprising: receiving, by a test monitor, the processed signal from the data collecting circuit via the connection interface since it is known in the art that a signal can be processed (View Lin ¶ 8). Such modification would have allowed a processed signal to determine operational status.
Yang and Lin do not explicitly teach encoding, by the test monitor, the processed signal to generate log information; and determining, by the test monitor, an operation status of the memory module according to the log information.
However, Storm teaches encoding, by the test monitor, the processed signal to generate log information (View Storm ¶ 16, 57; information can include error log information that can include a record of all errors experienced (either hardware errors, software errors, or both) by the memory device, persistent event log information, encoded operational mode information, relative time information (e.g., of events occurring within the memory sub-system), information corresponding to state machine monitoring, controller information, status bit information, and/or operational failure information associated with the memory device); and determining, by the test monitor, an operation status of the memory module according to the log information (View Storm ¶ 16, 54; retrieve information, such as signal information, log information, state information, etc. stored by the components of the memory sub-system to analyze the signal information, log information, and/or state information to determine potential causes that led to the failures and/or fault conditions experienced by the components of the memory sub-system in order to triage the memory sub-system or the components thereof).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with encoding, by the test monitor, the processed signal to generate log information; and determining, by the test monitor, an operation status of the memory module according to the log information since it is known in the art that log information can be generated (View Storm ¶ 16, 54). Such modification would have allowed a processed signal to be encoded to generate log information.
Claim 10, most of the limitations of this claim have been noted in the rejection of Claim 8. Yang further teaches transmitting the signal between the controller and the at least one memory chip via a circuit substrate of the memory module (View Yang ¶ 7, 8; semiconductor memory system includes a processor and a stacked memory which are mounted over a substrate including a plurality of external connection terminals), wherein the data collecting circuit receives the signal via the circuit substrate (View Yang ¶ 8; a test circuit is inserted into the semiconductor memory system and a test result obtained by the test circuit is checked through a test pin of the substrate).
Claim 11, most of the limitations of this claim have been noted in the rejection of Claim 8. Storm further teaches the processed signal is transmitted from the data collecting circuit to the test monitor via a transmission line coupled to the connection interface (View Storm ¶ 16; retrieve information, such as signal information, log information, state information, etc. stored by the components of the memory sub-system to analyze the signal information, log information, and/or state information to determine potential causes that led to the failures and/or fault conditions experienced by the components of the memory sub-system in order to triage the memory sub-system or the components thereof).
Claim 14, most of the limitations of this claim have been noted in the rejection of Claim 8. Storm further teaches storing, by the test monitor, the log information in a storage (View Storm ¶ 20; circuitry can control monitoring and analysis of signals, logs, and/or state information associated with the memory sub-system and/or a memory device of the memory sub-system and can aid in the extraction of such information in the event that the memory sub-system has experienced a failure and/or fault condition that has caused the memory sub-system to become inoperable).
Claim 15, most of the limitations of this claim have been noted in the rejection of Claim 14. Storm further teaches the storage is implemented by a hard disk drive (HDD) or a solid state drive (SSD) (View Storm ¶ 25; a memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD)).
Claim(s) 2 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Komura (US Patent Application 2009/0243627).
Claim 2, most of the limitations of this claim have been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach the data collecting circuit is configured to perform a frequency reduction on the signal to generate the processed signal.
However, Komura teaches the data collecting circuit is configured to perform a frequency reduction on the signal to generate the processed signal (View Komura ¶ 116, 117; the power consumption is reduced by including the frequency dividers and reducing the respective frequencies of the monitoring signal and the clock signal both supplied to the determination circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with the data collecting circuit is configured to perform a frequency reduction on the signal to generate the processed signal since it is known in the art that a signal frequency can be reduced (View Komura ¶ 116, 117). Such modification would have allowed a processed signal to be generated with a reduced frequency.
Claim 9, most of the limitations of this claim have been noted in the rejection of Claim 8. The combination of teachings does not explicitly teach performing, at the data collecting circuit, a frequency-down conversion on the signal to generate the processed signal.
However, Komura teaches performing, at the data collecting circuit, a frequency-down conversion on the signal to generate the processed signal (View Komura ¶ 116, 117; the power consumption is reduced by including the frequency dividers and reducing the respective frequencies of the monitoring signal and the clock signal both supplied to the determination circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with the data collecting circuit is configured to perform a frequency reduction on the signal to generate the processed signal since it is known in the art that a signal frequency can be reduced (View Komura ¶ 116, 117). Such modification would have allowed a processed signal to be generated with a reduced frequency.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Fukuda (US Patent Application 2006/0294422).
Claim 3, most of the limitations of this claim have been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach a frequency of the processed signal is lower than a frequency of the signal.
However, Fukuda teaches a frequency of the processed signal is lower than a frequency of the signal (View Fukuda ¶ 23; controlling may be achieved by regarding the processing section which operates in one of the plurality of clock signals which has a higher frequency, as the fault processing section, and the processing section which operates in one of the plurality of clock signals which has a lower frequency, as the normal processing section, when the detected power supply voltage is lower than the threshold value).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with a frequency of the processed signal is lower than a frequency of the signal since it is known in the art that a processed signal frequency can be reduced (View Fukuda ¶ 23). Such modification would have allowed a processed signal to be generated with a lower frequency.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Kao (US Patent Application 2024/0105360).
Claim 4, most of the limitations of this claim have been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach the connection interface is a Universal Serial Bus (USB) connection interface.
However, Kao teaches the connection interface is a Universal Serial Bus (USB) connection interface (View Kao ¶ 19; a card-type USB C transfer device includes a substrate, a first connection interface disposed on the substrate to couple and electrically connect with a portable power source, enabling the card-type USB C transfer device electrically coupled to the portable power source).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with the connection interface is a Universal Serial Bus (USB) connection interface since it is known in the art that a connection interface can be used (View Kao ¶ 19). Such modification would have allowed a connection interface to be used in the test system.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Kilewer (US Patent Application 2008/0141075).
Claim 5, most of the limitations of this claim have been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach each of the at least one memory chip is a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip.
However, Kilewer teaches each of the at least one memory chip is a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip (View Kilewer ¶ 71; test methods may be applied not only to DRAM memory chips but also to memory chips of other technologies. For example, to memory chips having separate data inputs and separate data outputs.).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with each of the at least one memory chip is a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip since it is known in the art that a memory chip can be a DRAM (View Kilewer ¶ 71). Such modification would have allowed a memory module to be tested.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Lee (US Patent Application 2017/0287535).
Claim 6, most of the limitations of this claim have been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach the signal is transmitted between the controller and the at least one memory chip in a unidirectional or bidirectional fashion.
However, Lee teaches the signal is transmitted between the controller and the at least one memory chip in a unidirectional or bidirectional fashion (View Lee ¶ 40; the first device may be a memory controller and the second device may be a memory device (e.g., a semiconductor memory chip or package that includes a memory cell array). FIG. 1 illustrates only components for unidirectional communication for convenience of illustration such that the first device functions as a transmitter and the second device functions as a receiver, but each of the first device and the second device may perform bidirectional communication).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with the signal is transmitted between the controller and the at least one memory chip in a unidirectional or bidirectional fashion since it is known in the art that a signal can be transmitted unidirectionally or bidirectionally (View Lee ¶ 40). Such modification would have allowed a signal to be transmitted between a controller and memory chip.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) and in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Wang (US Patent Application 2006/0143621).
Claim 7, most of the limitations of this claim have been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach the at least one memory chip is removably soldered on the circuit substrate.
However, Wang teaches the at least one memory chip is removably soldered on the circuit substrate (View Wang ¶ 21; Non-volatile memory and/or ROM can either be permanently attached (such as via soldering) to PC Card, or can be removably attached to PC Card (such as via the use of socketed chips)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with the at least one memory chip is removably soldered on the circuit substrate since it is known in the art that a memory chip can be removed (View Wang ¶ 21). Such modification would have allowed a memory chip to be removed from a circuit.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Zhu (US Patent Application 2019/0171598).
Claim 12, most of the limitations of this claim have been noted in the rejection of Claim 8. The combination of teachings does not explicitly teach calculating, by the test monitor, a core timing and a clock speed of the at least one memory chip.
However, Zhu teaches calculating, by the test monitor, a core timing and a clock speed of the at least one memory chip (View Zhu ¶ 26; measuring relative clock times in terms of core clock cycles versus in terms of interface clock cycles; the interface clock speed may run at any integer multiple of the core clock speed).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with calculating, by the test monitor, a core timing and a clock speed of the at least one memory chip since it is known in the art that timing and speed can be calculated (View Zhu ¶ 26). Such modification would have allowed a test monitor to calculate the timing and speed of the memory chip.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Patent Application 2014/0006863) in view of Lin (US Patent Application 2017/0164369) in view of Storm (US Patent Application 2024/0004752) and further in view of Han (US Patent Application 2012/0170125).
Claim 13, most of the limitations of this claim have been noted in the rejection of Claim 8. The combination of teachings does not explicitly teach determining the operation status comprises: determining whether commands transmitted between the controller and the at least one memory chip are legal and meet a Joint Electron Device Engineering Council (JEDEC) standard definition.
However, Han teaches determining the operation status comprises: determining whether commands transmitted between the controller and the at least one memory chip are legal and meet a Joint Electron Device Engineering Council (JEDEC) standard definition (View Han ¶ 54; according to definitions by international semiconductor association such as the Joint Electron Device Engineering Council (JEDEC) and the Electronic Industry Association of Japan (EIAJ), the chip scale package is generally a name for a class of packages having an area no larger than 1.2 times as large as that of a chip).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the combination of teachings with determining the operation status comprises: determining whether commands transmitted between the controller and the at least one memory chip are legal and meet a Joint Electron Device Engineering Council (JEDEC) standard definition since it is known in the art that a Joint Electron Device Engineering Council (JEDEC) standard definition can be used (View Han ¶ 54). Such modification would have allowed a command to meet the Joint Electron Device Engineering Council (JEDEC) standard definition.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Treue et al. (U.S. Patent 7,231,551); teaches encoded state signal.
Meaney et al. (U.S. Patent Application 2004/0139374); teaches error status signal.
Conclusion
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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