DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features “wherein the 2-1st sub-transistor is connected between the 2-2nd node and the 2-2nd sub-transistor, and wherein the 2-2nd sub-transistor is connected between the 1-2nd node and the 2-1st sub-transistor” and “wherein the 1-1st sub-transistor is connected between the 2-1st node and the 1-2nd sub-transistor, and wherein the 1-2nd sub-transistor is connected between the 1-1st node and the 1-1st sub-transistor” of claims 4, 5, and 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 5, and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 and 7 recites “wherein the 2-1st sub-transistor is connected between the 2-2nd node and the 2-2nd sub-transistor, and wherein the 2-2nd sub-transistor is connected between the 1-2nd node and the 2-1st sub-transistor”. However, neither the drawings and nor the specifications explains such connections. Figs. 5-8 only shows wherein the 2-1st sub-transistor is connected between the 1-2nd node and the 2-2nd sub-transistor, and wherein the 2-2nd sub-transistor is connected between the 2-2nd node and the 2-1st sub-transistor, and not as recited in claims 4 and 7.
For the purpose of examination of claims 4 and 7 it is interpreted as “wherein the 2-1st sub-transistor is connected between the 1-2nd node and the 2-2nd sub-transistor, and wherein the 2-2nd sub-transistor is connected between the 2-2nd node and the 2-1st sub-transistor”.
Claim 5 recites “wherein the 1-1st sub-transistor is connected between the 2-1st node and the 1-2nd sub-transistor, and wherein the 1-2nd sub-transistor is connected between the 1-1st node and the 1-1st sub-transistor”. However, neither the drawings and nor the specifications explains such connections. Figs. 5-8 only shows wherein the 1-1st sub-transistor is connected between the 1-1st node and the 1-2nd sub-transistor, and wherein the 1-2nd sub-transistor is connected between the 2-1st node and the 1-1st sub-transistor, and not as recited in claim 5.
For the purpose of examination of claim 5 it is interpreted as “wherein the 1-1st sub-transistor is connected between the 1-1st node and the 1-2nd sub-transistor, and wherein the 1-2nd sub-transistor is connected between the 2-1st node and the 1-1st sub-transistor”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 12-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 20210210020) in the view of Lee (US 20070001938).
Regarding claim 1: Cho teaches a display device (Fig. 4 shows a display device #DD) comprising: a first pixel including a first pixel circuit and a first light emitting element; a second pixel including a second pixel circuit and a second light emitting element; and a data line configured to receive a data signal (Figs. 4-5 and paragraph [0080-0097] a plurality of pixels PX including a first pixel circuit for first pixel and a second pixel circuit for second adjacent pixel, and both of the pixel circuits comprises its own light emitting elements LD, and a data line DL configured to receive a data signal), wherein the first pixel circuit comprises: a 1-1st transistor including a gate electrode connected to a 1-1st node and connected between a first power source line receiving a first power voltage, and a 2-1st node; a 2-1st transistor connected to the data line and receiving a first scan signal; and a 3-1st transistor connected between the 1-1st node and the 2-1st node, wherein the 3-1st transistor comprises: a 1-1st sub-transistor receiving a second scan signal; and a 1-2nd sub-transistor receiving the first scan signal (Figs. 4-5 and paragraph [0080-0097] teach each of the pixel circuit comprises a 1st transistor T1 including a gate electrode G1 connected to a 1st node RN and connected between a first power source line receiving a first power voltage ELVDD, and a 2-1st node connected drain D1 of T1; a 2-1st transistor T2 connected to the data line DL and receiving a first scan signal SCi; and a 3-1st transistor T3 connected between the 1-1st node RN and the 2-1st node, wherein the 3-1st transistor T3 comprises: a 1-1st sub-transistor receiving a second scan signal SC; and a 1-2nd sub-transistor receiving the first scan signal SC), wherein the second pixel circuit comprises: a 1-2nd transistor including a gate electrode connected to a 1-2nd node and electrically connected between a 2-2nd node and the first power source line; a 2-2nd transistor connected to a data line and receiving the first scan signal; and a 3-2nd transistor connected between the 1-2nd node and the 2-2nd node, wherein the 3-2nd transistor comprises: a 2-1st sub-transistor receiving the first scan signal; and a 2-2nd sub-transistor receiving the second scan signal (Figs. 4-6 and paragraph [0080-0097] teach construction of the second pixel circuit is similar to the first pixel circuit as explained above so it also comprises a 1-2nd transistor T1 including a gate electrode G1 connected to a 1-2nd node RN and electrically connected between a 2-2nd node and the first power source line ELVDD, as explained above; a 2-2nd transistor T2 connected to a data line DL and receiving the first scan signal SC; and a 3-2nd transistor T3 connected between the 1-2nd node RN and the 2-2nd node, wherein the 3-2nd transistor T3 comprises: a 2-1st sub-transistor receiving the first scan signal SC; and a 2-2nd sub-transistor receiving the second scan signal SC).
Cho does not explicitly states a same data line shared between the two adjacent pixel circuits and a 2-2nd sub-transistor receiving the second scan signal that is delayed by a predetermined time.
However, Lee discloses a same data line shared between the two adjacent pixel circuits and a 2-2nd sub-transistor receiving the second scan signal that is delayed by a predetermined time (Fig. 3 and paragraph [0019-0030] teach a same data line D shared between the two adjacent pixel circuits OP & EP and a 2-2nd sub-transistor SW_E1 receiving the second scan signal S(n+1) that is delayed by a predetermined time). It would have been obvious for a person skilled in the art before the effective filing date of the invention to modify Cho’s invention by including above teachings of Lee, because utilizing the same data line among the adjacent pixels requires less wiring lines and using delayed scan signal is known in the art for adjacent pixel to achieve optimal/desired image quality and simplifying pixel circuit design, as taught by Lee. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claims 2 & 18: Cho teaches wherein the 1-1st sub-transistor is connected between the 1-1st node and the 1-2nd sub-transistor, and wherein the 1-2nd sub-transistor is connected between the 2-1st node and the 1-1st sub-transistor (Fig. 5 and paragraph [0080-0097] #T3 with two 1st and 2nd sub-transistors for both pixels connected as claimed and as explained in claim 1 rejection).
Regarding claims 3, 6, & 19: Cho teaches wherein the 2-1st sub-transistor is connected between the 1-2nd node and the 2-2nd sub-transistor, and wherein the 2-2nd sub-transistor is connected between the 2-2nd node and the 2-1st sub-transistor (Fig. 5 and paragraph [0080-0097] #T3 with two 1st and 2nd sub-transistors for both pixels connected as claimed and as explained in claim 1 rejection).
Regarding claims 4 & 7: Cho teaches wherein the 2-1st sub-transistor is connected between the 2-2nd node and the 2-2nd sub-transistor, and wherein the 2-2nd sub-transistor is connected between the 1-2nd node and the 2-1st sub-transistor (Fig. 5 and paragraph [0080-0097] #T3 with two 1st and 2nd sub-transistors for both pixels connected as claimed and as explained in claim 1 rejection, also see 112 rejection).
Regarding claim 5: Cho teaches wherein the 1-1st sub-transistor is connected between the 2-1st node and the 1-2nd sub-transistor, and wherein the 1-2nd sub-transistor is connected between the 1-1st node and the 1-1st sub-transistor (Fig. 5 and paragraph [0080-0097] #T3 with two 1st and 2nd sub-transistors for both pixels connected as claimed and as explained in claim 1 rejection, also see 112 rejection).
Regarding claim 8: Cho teaches wherein the first light emitting element is connected between the 2-1st node and a second power source line receiving a second power voltage having a different voltage level from a voltage level of the first power voltage (Fig. 5 and paragraph [0080-0097] teach the light emitting element for both pixels connected between the 2-1st node and a second power source line ELVSS having a different voltage level from a voltage of the first power voltage ELVDD).
Regarding claim 9: Cho teaches wherein when viewed from above a plane, the first light emitting element overlaps the first pixel circuit, and the second light emitting element is positioned in a region offset from the second pixel circuit (Figs. 8A-B and paragraph [0140-0148] teach the pixels can be designed in multiple different configuration including the first light emitting elements overlap the first pixel circuit as shown in Fig. 8A, and the second light emitting element can be positioned in region offset from the second pixel circuit as shown in Fig. 8B).
Regarding claim 12: Cho teaches wherein the first pixel circuit further comprises: a 4-1st transistor receiving a third scan signal and connected between the 1-1st node and a first voltage line receiving a first initialization voltage; a 5-1st transistor receiving an emission control signal and connected between the first power source line and the 1-1st transistor; a 6-1st transistor receiving the emission control signal and connected between the first light emitting element and the 1-1st transistor; and a 7-1st transistor receiving the first scan signal and connected between the first light emitting element and a second voltage line receiving a second initialization voltage (Fig. 5 and paragraph [0080-0097] teach the first pixel circuit comprises a 4-1st transistor T4 receiving a third scan signal Sci-1 between the 1-1st node RN and a first initialization voltage VINIT; a 5-1st transistor T5 receiving an emission control signal Ei and connected between the first power source line ELVDD and the 1-1st transistor T1; a 6-1st transistor T6 receiving the emission control signal Ei and connected between the first light emitting element LD and the 1-1st transistor T1; and a 7-1st transistor T7 receiving the first scan signal ISCi and connected between the first light emitting element LD and a second voltage line receiving a second initialization voltage VINIT).
Regarding claim 13: Combination of Cho and Lee teach wherein the first scan signal is a signal obtained by delaying the third scan signal by a predetermined time (Cho in Fig. 6 and paragraph [0099-0109] and Lee in Figs. 5, 7 and paragraph [0031-0043] teach a plurality of scan signals and the first scan signal can be obtained by delaying the other scan signal including third scan signal). See claim 1 rejection for combination reasoning of Cho and Lee, same rationale applies here.
Regarding claim 14: Cho teaches wherein during a first data write period, the first scan signal and the second scan signal are activated to turn on the 3-1st transistor, and wherein during the first data write period, the 1-1st node is at a voltage obtained by subtracting a threshold voltage of the 1-1st transistor from a first voltage of the data signal (Fig. 5 and paragraph [0080-0097] teach scan signals used to activate T3 transistor as claimed).
Claim 17: Claim 17 recites similar claim limitations as in claim 1. Thus, all the arguments made above for claim 1 are applicable for claim 17.
Regarding claim 20: Cho teaches an electronic device comprising: a display panel (Fig. 4 shows a display device #DD) comprising: a first pixel comprising a first pixel circuit and a first light-emitting element; a second pixel comprising a second pixel circuit and a second light-emitting element; a scan driver configured to provide a first scan signal and a second scan signal (Figs. 4-5 and paragraph [0080-0097] a plurality of pixels PX including a first pixel circuit for first pixel and a second pixel circuit for second adjacent pixel, and both of the pixel circuits comprises its own light emitting elements LD, and a scan driver SDC configured to provide the plurality of scan signals), wherein the first pixel circuit comprises: a first driving transistor including a gate electrode connected to a first node and connected between a first power source line and a second node; a first switch transistor connected to a data line and configured to receive the first scan signal; and a first charge transfer transistor connected between the first node and the second node and configured to receive the first scan signal and the second scan signal (Figs. 4-5 and paragraph [0080-0097] teach each of the pixel circuit comprises a first driving transistor T1 including a gate electrode connected to a first node RN and connected between a first power source line ELVDD and a second node connected drain D1 of T1; a first switch transistor T2 connected to a data line DL and configured to receive the first scan signal Sci; and a first charge transfer transistor T3 connected between the first node RN and the second node and configured to receive the first scan signal and the second scan signal at two gates G3-1 and G3-2), wherein the second pixel circuit comprises: a second driving transistor including a gate electrode connected to a third node and connected between a fourth node and the first power source line; a second switch transistor connected to the data line and configured to receive the first scan signal; and a second charge transfer transistor connected between the third node and the fourth node and configured to receive the first scan signal and the second scan signal that is delayed by a predetermined time (Figs. 4-6 and paragraph [0080-0097] teach construction of the second pixel circuit is similar to the first pixel circuit as explained above so it also comprises a second driving transistor T1 including a gate electrode connected to a third node RN and connected between a fourth node connected drain D1 of T1 and the first power source line ELVDD; a second switch transistor T2 connected to the data line DL and configured to receive the first scan signal SCi; and a second charge transfer transistor T3 connected between the third node and the fourth node and configured to receive the first scan signal and the second scan signal at two gates G3-1 and G3-2).
Cho does not explicitly states a same data line shared between the two adjacent pixel circuits and the second scan signal that is delayed by a predetermined time.
However, Lee discloses a same data line shared between the two adjacent pixel circuits and the second scan signal that is delayed by a predetermined time (Fig. 3 and paragraph [0019-0030] teach a same data line D shared between the two adjacent pixel circuits OP & EP and a 2-2nd sub-transistor SW_E1 receiving the second scan signal S(n+1) that is delayed by a predetermined time). It would have been obvious for a person skilled in the art before the effective filing date of the invention to modify Cho’s invention by including above teachings of Lee, because utilizing the same data line among the adjacent pixels requires less wiring lines and using delayed scan signal is known in the art for adjacent pixel to achieve optimal/desired image quality and simplifying pixel circuit design, as taught by Lee. The rationale would have been to use a known method or technique to achieve predictable results.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 20210210020), in the view of Lee (US 20070001938), and further in the view of Kim (US 20180174511).
Regarding claim 10: Combination of Cho and Lee do not explicitly disclose wherein the first light emitting element and the second light emitting element emit light of a same color.
However, However Kim teaches wherein the first light emitting element and the second light emitting element emit light of a same color (Figs. 3-4 and paragraph [0029-0053] teach the first and second light emitting elements of pixel Sp11 sharing the data line DL2 with pixel SP22 are of a same color). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Cho and Lee, by including above teachings of Kim, because same color pixels arranged to share the same data line requires less wiring lines while achieving optimal/desired image quality and simplifying pixel circuit design, as taught by Kim. The rationale would have been to use a known method or technique to achieve predictable results.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 20210210020), in the view of Lee (US 20070001938), and further in the view of Seo (US 20160189609).
Regarding claim 11: Combination of Cho and Lee do not explicitly disclose a first extension wire connected between the first light emitting element and the first pixel circuit; and a second extension wire connected between the second light emitting element and the second pixel circuit, wherein a length of the first extension wire is shorter than a length of the second extension wire.
However, Seo teaches a first extension wire connected between the first light emitting element and the first pixel circuit; and a second extension wire connected between the second light emitting element and the second pixel circuit, wherein a length of the first extension wire is shorter than a length of the second extension wire (Fig. 5 and paragraph [0081-0087] teach plurality of extension wires or anode connecting the OLED to the pixel circuit, and the first extension wire or AnodeJ is shorter than a length of the second extension wire AnodeK). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Cho and Lee, by including above teachings of Seo, because using different length extension wires requires less wiring overall while achieving optimal/desired image quality and simplifying pixel circuit design, as taught by Seo. The rationale would have been to use a known method or technique to achieve predictable results.
Allowable Subject Matter
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15: None of the cited prior arts either alone and/or in combination teach “wherein during a second data write period different from the first data write period, the first scan signal and the second scan signal delayed by the predetermined time are activated to turn on the 3-2nd transistor, and wherein during the second data write period, the 1-2nd node is at a voltage obtained by subtracting a threshold voltage of the 1-2nd transistor from a second voltage of the data signal”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIT CHATLY whose telephone number is (571)270-1610. The examiner can normally be reached Mon-Fri 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 5712707230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMIT CHATLY/Primary Examiner, Art Unit 2624
Prosecution Insights