Prosecution Insights
Last updated: July 14, 2026
Application No. 19/263,178

DRIVER CIRCUIT AND DISPLAY DEVICE

Non-Final OA §102§103
Filed
Jul 08, 2025
Priority
Jul 09, 2024 — JP 2024-110454
Examiner
PERVAN, MICHAEL
Art Unit
2629
Tech Center
2600 — Communications
Assignee
Sharp Display Technology Corporation
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
1y 6m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
752 granted / 928 resolved
+19.0% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
15 currently pending
Career history
939
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
73.3%
+33.3% vs TC avg
§102
14.8%
-25.2% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 928 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Takahashi et al (US 2013/0093743). In regards to claim 1, Takahashi discloses a driver circuit for driving a plurality of signal lines, the driver circuit (gate driver 400) comprising a plurality of unit circuits (stage constituent circuits SR(1) - SR(i)) including an nth unit circuit (Figs. 1-4 and paragraphs 210-211, 216), wherein the nth unit circuit includes a clock terminal (input terminal 41) through which a clock signal (first clock CKA) is inputted, a setting terminal (output terminal 52) through which a setting signal (different stage control signal Z) is outputted to another unit circuit, a setting transistor (transistor M6) connected to the clock terminal and the setting terminal, a control node (second node N2), a control capacitor (capacitor C2), and a control transistor (transistor M9) whose gate terminal is connected to the control node (Fig. 1 and paragraphs 216-218), the control node is connected to a first conducting terminal of the control transistor via the control capacitor (Fig. 1 and paragraphs 216-218), and a second conducting terminal of the control transistor is connected to the clock terminal (Fig. 1 and paragraphs 216-218). In regards to claim 4, Takahashi discloses the driver circuit according to Claim 1, wherein a gate terminal of the setting transistor is connected to the control node (Fig. 1 and paragraphs 216-218). In regards to claim 5, Takahashi discloses the driver circuit according to Claim 1, wherein in a set period, the setting transistor is turned on and the control capacitor is charged by the control node becoming active, and the control node is boosted by the clock signal rising (paragraphs 222-228). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al (US 2013/0093743) in view of Hu et al (CN 116524837). In regards to claim 20, Takahashi discloses a display device comprising: the driver circuit according to Claim 1 (refer to claim 1), and wherein the plurality of signal lines are scanning lines (gate bus lines GL1-GLi) (Fig. 2 and paragraph 208), a first driving signal is a scan signal (scanning signal GOUT) (Fig. 1 and paragraph 216), and the plurality of signal lines are formed in the display unit (Figs. 2-3 and paragraphs 204). Takahashi does not disclose a display unit that is capable of setting refresh rates on an area-by-area basis. Hu discloses a display unit that is capable of setting refresh rates on an area-by-area basis (Abstract and pages 12-13). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi with the teachings of Hu, a display with area-by-area refresh rates, because it would reduce power consumption of the display. Allowable Subject Matter Claims 2-3 and 6-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Umezaki et al (US 2011/0221734; provided by Applicant) discloses a display device in which rewriting of only a given section of an image can be achieved or to simplify the configuration of a circuit including wirings in a display device in which partial driving can be performed. A shift of a selection signal in a shift register included in a scan line driver circuit and supply of a selection signal to scan lines are controlled independently of each other, so that rewriting of only a given section of an image can be achieved. The above operation is realized by providing a wiring that supplies a signal representing a clock signal or a fixed potential. Therefore, the configuration of the circuit including the wiring can be simplified in the display device including the wiring while partial driving can be performed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael Pervan whose telephone number is (571)272-0910. The examiner can normally be reached Mon - Fri between 7:00am - 4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at (571) 272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL PERVAN/Primary Examiner, Art Unit 2629 April 2, 2026
Read full office action

Prosecution Timeline

Jul 08, 2025
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12675174
STYLUS AND ELECTRONIC DEVICE ASSEMBLY
2y 9m to grant Granted Jul 07, 2026
Patent 12675198
Input Device
1y 3m to grant Granted Jul 07, 2026
Patent 12658082
DISPLAY DEVICE AND DRIVING METHOD THEREOF
2y 5m to grant Granted Jun 16, 2026
Patent 12656923
DISPLAY DEVICE
1y 2m to grant Granted Jun 16, 2026
Patent 12658090
ARRAY SUBSTRATE AND DISPLAY PANEL COMPRISING THE SAME
1y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
88%
With Interview (+7.1%)
2y 6m (~1y 6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 928 resolved cases by this examiner. Grant probability derived from career allowance rate.

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