Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
First 102 rejection
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,864,718 to Yu.
With respect to claim 1, Yu discloses in Fig. 3 a voltage level shifter, comprising:
a voltage level shift circuit (e.g., MP11, MP21, MN11, MN21, MN12, and MN22), comprising a first boost input terminal (e.g., N1), a second boost input terminal (e.g., N2), a first reference input terminal (e.g., IN) and a second reference input terminal (e.g., /IN), and operating between a first voltage (e.g., VDDH) and a second voltage (e.g., ground); and
a boost circuit (e.g., MN13, MN23, MP12, and MP22), coupled to the voltage level shift circuit, and configured to pre-charge the first boost input terminal (e.g., N1) and the second boost input terminal (e.g., N2) to a third voltage value (e.g., VDDL), and to boost the third voltage value (e.g., VDDL) to a fourth voltage value according to a pair of differential signals provided to the first reference input terminal (e.g., IN) and the second reference input terminal (e.g., /IN).
With respect to claim 2, the boost circuit (e.g., MN13, MN23, MP12, and MP22) comprises: a first boost circuit (e.g., MN13 and MP12) block, coupled to the first boost input terminal (e.g., N1) and the first reference input terminal (e.g., IN), and configured to receive a supply voltage (e.g., VDDL); and a second boost circuit (e.g., MN23 and MP22) block, coupled to the second boost input terminal (e.g., N2) and the second reference input terminal (e.g., /IN), and configured to receive the supply voltage (e.g., VDDL).
With respect to claim 3, the supply voltage (e.g., VDDL) has the third voltage value (e.g., VDDL).
With respect to claim 4, the first boost circuit (e.g., MN13 and MP12) block comprises: a first transistor (e.g., MN13), having a control terminal and a first terminal to receive the supply voltage (e.g., VDDL); and a first capacitor (e.g., MP12), having a first terminal coupled to a second terminal of the first transistor and the first boost input terminal (e.g., N1), wherein a second terminal of the first capacitor (e.g., MP12) is coupled to the first reference input terminal (e.g., IN).
With respect to claim 5, the second boost circuit (e.g., MN23 and MP22) block comprises: a second transistor (e.g., MN23), having a control terminal and a first terminal to receive the supply voltage (e.g., VDDL); and a second capacitor (e.g., MP22), having a first terminal coupled to a second terminal of the second transistor (e.g., MN23) and the second boost input terminal (e.g., N2), wherein a second terminal of the second capacitor (e.g., MP22) is coupled to the second reference input terminal (e.g., /IN).
With respect to claim 6, the voltage level shift circuit comprises: a pair of cross-coupled transistors (e.g., MP11, MP21, MN11, and MN21), having the first boost input terminal (e.g., N1) and the second boost input terminal (e.g., N2), and configured to receive the first voltage (e.g., VDDH); and a pair of differential transistors (e.g., MN12 and MN22), coupled to the pair of cross-coupled transistors (e.g., MP11, MP21, MN11, and MN21), having the first reference input terminal (e.g., IN) and the second reference input terminal (e.g., /IN), and configured to receive the second voltage (e.g., ground).
With respect to claim 7, the pair of cross-coupled transistors (e.g., MP11, MP21, MN11, and MN21) comprise: a third transistor (e.g., MP11), having a first terminal to receive the first voltage (e.g., VDDH); a fourth transistor (e.g., MP21), having a first terminal to receive the first voltage (e.g., VDDH); a fifth transistor (e.g., MN11), having a control terminal serving as the first boost input terminal (e.g., N1), wherein a first terminal of the fifth transistor (e.g., MN11) is coupled to a second terminal of the third transistor (e.g., MP11), and a second terminal of the fifth transistor (e.g., MN11) is coupled to (e.g., via MN11) a control terminal of the fourth transistor (e.g., MP21) and the pair of differential transistors (e.g., MN12 and MN22); and a sixth transistor (e.g., MN21), having a control terminal serving as the second boost input terminal (e.g., N2), wherein a first terminal of the sixth transistor (e.g., MN21) is coupled to a second terminal of the fourth transistor (e.g., MP21), and a second terminal of the sixth transistor (e.g., MN21) is coupled to (e.g., via MN21) a control terminal of the third transistor (e.g., MP11) and the pair of differential transistors (e.g., MN12 and MN22).
With respect to claim 8, the pair of differential transistors (e.g., MN12 and MN22) comprises: a seventh transistor (e.g., MN12), having a control terminal serving as the first reference input terminal (e.g., IN), wherein a first terminal of the seventh transistor (e.g., MN12) is coupled to the second terminal of the fifth transistor (e.g., MN11) and the control terminal of the fourth transistor (e.g., MP21), and a second terminal of the seventh transistor (e.g., MN12) is configured to receive the second voltage (e.g., ground); and an eighth transistor (e.g., MN22), having a control terminal serving as the second reference input terminal (e.g., /IN), wherein a first terminal of the eighth transistor (e.g., MN22) is coupled to the second terminal of the sixth transistor (e.g., MN21) and the control terminal of the third transistor (e.g., MP11), and a second terminal of the eighth transistor (e.g., MN22) is configured to receive the second voltage (e.g., ground).
With respect to claim 9, respective sizes of the first transistor (e.g., MN13) and the second transistor (e.g., MN23) is different from a size (e.g., compared to thick oxide devices MN11 and MN21 per Col. 3 l. 8-10, thin oxide devices MN13 and MN23 per Col. 2 ll. 53-54 have a different size) from the fifth transistor (e.g., MN11).
Second 102 rejection
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0302066 to Chen.
With respect to claim 1, Chen discloses in Fig. 2 a voltage level shifter, comprising:
a voltage level shift circuit (e.g., 110), comprising a first boost input terminal (e.g., P1), a second boost input terminal (e.g., P2), a first reference input terminal (e.g., IN3) and a second reference input terminal (e.g., IN5), and operating between a first voltage (e.g., VH) and a second voltage (e.g., VSS); and
a boost circuit (e.g., MN3, MN5, and C1-C2), coupled to the voltage level shift circuit, and configured to pre-charge the first boost input terminal (e.g., P1) and the second boost input terminal (e.g., P2) to a third voltage value (e.g., VCC), and to boost the third voltage value (e.g., VCC) to a fourth voltage value according to a pair of differential signals provided to the first reference input terminal (e.g., IN3) and the second reference input terminal (e.g., IN5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu.
With respect to claim 10, while Yu discloses in Fig. 3 the first reference input terminal (e.g., IN) and the second reference input terminal (e.g., /IN), Yu fails to disclose that /IN is provided by using an inverter receiving IN. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that an inverting input for a differential input pair may be provided through an inverter receiving an input; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide /IN in Fig. 3 of Yu using the notoriously well-known method of providing an inverting input for a differential input pair using an inverter receiving an input because providing inverting input /IN in Fig. 3 of Yu requires a specific implementation and the notoriously well-known method provides such a specific implementation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2836
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